Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs--AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...

Abstract — Optical interconnection through stacked silicon foundry complementary metal–oxide–semiconductor (CMOS) circuitry has been demonstrated at a data rate of over 40 Mb/s with an open eye diagram. The system consists of a 0.8-"m transmitter and receiver realized in foundry digital CMOS. The use of digital CMOS enables on-chip integration with more complex digital systems, such as a microprocessor. Two layers of these circuits were integrated with thin-film InP-based light emitting diodes and metal-semiconductor-metal photodetectors operating at 1.3 "m (to which the silicon is transparent) to enable vertical optical through-Si communication between the stacked silicon circuits. Index Terms—Interconnections, integrated optoelectronics, optical, 3-D systems. I.