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Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
 in Proc. of 16th International Conference on VLSI Design
, 2003
"... In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we ..."
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Cited by 18 (10 self)
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In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number of constraints. By introducing two additional variables per gate, namely, the fastest and the slowest arrival times, besides the gate delay,we reduce the number of the LP constraints to be linear in circuit size. For example, the 469gate c880 circuit requires 3,611 constraints as compared to the 6.95 million constraints needed with the previous method. The reduced constraints provably produce the same exact LP solution as obtained by the exponential set of constraints. For the rst time, we are able to optimize all ISCAS'85 benchmarks. For the c7552 circuit, when the input to output delay is constrained not to increase, a design with 366 delay bu ers consumes only 34 % peak and 38 % average power as compared to an unoptimized design. As shown in previous work, the use of delay bu ers is essential in this case. The practicality of the design is demonstrated by implementing an optimized 4bit ALU circuit for which the power consumption was obtained by a circuitlevel simulator. 1.
InputSpecific Dynamic Power Optimization for VLSI Circuits
 Proc. the International Symposium on Low Power Electronics and Design
, 2006
"... Literature proposes linear programming (LP) methods for glitchless design of digital circuits. Considering the worstcase these methods ensure absence of glitches for any arbitrary state of primary input as well as internal signals. In this paper, we examine an unexplored aspect, i.e., glitchfree de ..."
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Cited by 6 (1 self)
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Literature proposes linear programming (LP) methods for glitchless design of digital circuits. Considering the worstcase these methods ensure absence of glitches for any arbitrary state of primary input as well as internal signals. In this paper, we examine an unexplored aspect, i.e., glitchfree design with respect to a specific set of vectors (patterns). Introducing the logiclevel concepts of glitchgeneration patterns and glitchgeneration probability, which are analyzable through logic simulation, we remove glitch filtering requirements from gates on which the given set of input vectors cannot produce glitches. We relax constraints of any existing LP either selectively or probabilistically. Such inputspecific design from an LP model without process variation and another with process variation reduced the number of delay buffer overhead by up to 80 % and 63%, respectively, while maintaining the power reduction and overall delay.
Design of variable input delay gates for low dynamic power circuits
 PROC. THE INTERNATIONAL WORKSHOP ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION
, 2005
"... The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offe ..."
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Cited by 4 (0 self)
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The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multiinput CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different inputoutput paths through it, is known as a v ¯ ariable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called v ¯ ariable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.
Variable Input Delay CMOS Logic for Low Power Design
 Auburn University
, 2005
"... Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same i ..."
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Cited by 4 (0 self)
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Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. We propose a new gate design that has different delays along various input to output paths within the gate. This is accomplished by inserting selectively sized “permanently on ” series transistors at the inputs of the logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitchfree minimum dynamic power implementation of a digital circuit. Applying a previously described linear programming method to the c7552 benchmark circuit, we obtained a power saving of 58 % over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. All circuits had the same overall delay. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers. 1
Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits
 in Proc. 15th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS’05
, 2005
"... A gate that offers different delays for different inputoutput paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by ..."
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Cited by 2 (1 self)
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A gate that offers different delays for different inputoutput paths through it, is known as a variable input delay (VID) gate. The upper bound on this differential delay capability is specified by the parameter “ub”. These gates can be used to minimize the active power of a digital CMOS circuit by a path balancing and glitch filtering techniques discussed in recent publications. In this paper, we describe transistor sizing methods for three types of VID gates that satisfy given delay requirements. The three ways to obtain the differential delays are capacitance manipulation, nMOS transistor insertion, and CMOS transmission gate insertion. We also describe techniques for calculating the ub of each VID gate type. Finally, we outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance. 1
Total Power Minimization in GlitchFree CMOS Circuits Considering Process Variation
"... Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path ..."
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Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by deterministic glitch elimination (using hazard filtering and path balancing) increases because glitches randomly start reappearing under the influence of process variation. Combining existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which combines glitch elimination and dualthreshold design to statistically minimize the total power in a glitchfree circuit under process variation. 1.
Total Power Minimization in GlitchFree CMOS Circuits Considering Process Variation
, 2008
"... Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filt ..."
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Compared to subthreshold leakage, dynamic power is normally much less sensitive to the process variation due to its approximately linear relation to the process parameters. However, the average dynamic power of a circuit optimized by a deterministic path balancing approach increases because the filtered glitches randomly start reappearing under the influence of process variation. Combining several existing techniques, we propose a new statistical mixed integer linear programming (MILP) formulation, which uses path balancing and dualthreshold techniques to statistically minimize the total power in glitchfree circuits considering process variation.
A Generalized Minimum Dynamic Power and HighSpeed Design Methods for . . .
, 2004
"... We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays a ..."
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We formulate a linear program (LP) to simultaneously minimize the dynamic power and overall delay of a CMOS circuit. To eliminate all glitches either without or with minimal number of delay buffers, a CMOS gate is assumed to have adjustable input to output delays for each input. Since these delays are not independent, a transistor sizing problem would require very complex nonlinear optimization. We solve the problem in three steps. First, CMOS gates are analyzed to determine the realizable maximum differential input delay, ub, for the device technology being used. Second, an LP assumes the gate input and output delays as independent variables and determines them for all gates. This LP satisfies (1) glitch elimination conditions and the realizability constraint (ub) for all gates, and (2) the specified overall delay for the circuit. The total number of constraints in our LP is a linear function of the circuit size. Third, all gates are designed with the delays determined by the LP. As a sample result, using ub =10 when we designed the c1355 benchmark circuit specifying a large overall delay, a zero buffer design was obtained. It consumed 33 % power and had three times the overall delay as compared to an unoptimized design. When the overall delay was constrained not to increase, the lowpower design required 64 delay bu ers and consumed 37% power.