In recognition of the fundamental relation between regular arrays and systems of affine recurrence equations, the Alpha language was developed as the basis of a computer aided design methodology for regular array architectures. Alpha is used to initially specify algorithms at a very high algorithmic level. Regular array architecures can then be derived from the algorithmic specification using a transformational approach supported by the Alpha environment. This design methodology guarantees the final design to be correct by construction, assuming the initial algorithm was correct. In this paper, we address the problem of validating an initial specification. We demonstrate a translation methodolody which compiles Alpha into the imperative sequential language C. The C-code may then be compiled and executed to test the specification. We show how an Alpha program can be naively implemented by viewing it as a set of monolithic arrays and their filling functions, implemented usin...

: Alpha is a data parallel functional language which has the capability of specifying algorithms at a very high level. Our ultimate objective is to generate efficient parallel imperative code from an Alpha program. In this paper, we discuss the related problem of generating efficient single processor imperative code. Analysis techniques that were developed for the synthesis of systolic arrays are extended and adapted for the compilation of functional programming languages. We also demonstrate how a transformational methodology can be used as a compilation engine to transform an Alpha program to a sequential form. C--code is then generated using a straightforward pretty printer from the sequential form Alpha program. The C--code may then be compiled to efficiently execute the program. Key-words: parallelizing compilers, functional languages (R'esum'e : tsvp) Supported by NSF grant MIP-910852 and Esprit Basic Research Action NANA2, Number 6632 email: quinton@irisa.fr email: rajopadh@...

: We address the problem of computation upon ZZ-polyhedra which are intersections of polyhedra and integral lattices. We introduce a canonic representation for ZZ-polyhedra which allow to perform comparisons and transformations of ZZ-polyhedra with the help of a computational kernel on polyhedra. This contribution is a step toward the manipulation of images of polyhedra by affine functions, and has application in the domain of automatic parallelization and parallel vlsi synthesis. Key-words: regular parallelism, polyhedron, lattices, loop nest, Automatic synthesis methodology, vlsi (R'esum'e : tsvp) CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE Centre National de la Recherche Scientifique Institut National de Recherche en Informatique (URA 227) Universit e de Rennes 1 -- Insa de Rennes et en Automatique -- unit e de recherche de Rennes Manipulations de Z-poly`edres R'esum'e : Nous nous int'eressons au probl`eme du calcul sur les ZZ-poly`edres (intersections entre des poly`edres et...

. In this paper we present the affine clock calculus as an extension of the formal verification techniques provided by the Signal language. A Signal program describes a system of clock synchronisation constraints the consistency of which is verified by compilation (clock calculus) . Well-adapted in control-based system design, the clock calculus has to be extended in order to enable the validation of Signal-Alpha applications which usually contain important numerical calculations. The new affine clock calculus is based on the properties of affine relations induced between clocks by the refinement of Signal-Alpha specifications in a codesign context. Affine relations enable the derivation of a new set of synchronisability rules which represent conditions against which synchronisation constraints on clocks can be assessed. Properties of affine relations and synchronisability rules are derived in the semantical model of traces of Signal. A prototype implementing a subset of t...

In this paper we present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following paper are: (1) the class of piecewise regular algorithms is extended by allowing run-time dependent conditionals, (2) a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms, and (3) in order to achieve highest performance, we present a speculative scheduling approach. The results are applied to an illustrative example.

The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co-processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long instruction word) processors, their controller, local memory, and interfaces. The system also modifies the user's application software to make use of the generated accelerator. The user indicates the throughput to be achieved by specifying the number of processors and their initiation interval. In experimental comparisons, PICO-N designs are slightly more costly than hand-designed accelerators with the same performance.

: In this paper we present affine transformations as an extension of the Signal language for the specification and validation of real-time applications. A Signal program is a system of equations which specify dependencies between program data and synchronization constraints on clock variables. In order to test if a program is functionally safe, the Signal compiler resolves the clock constraints and verifies that the data dependency graph contains no cycles. By means of the new transformations, affine relations can be defined between clock variables and it gets necessary to enhance the compiler with facilities for the resolution of synchronization constraints on these clocks. To tackle these constraints, we propose an extension of the compiler based essentially on a canonical form of the affine relations. This extension removes some of the limits of the existing compiler and enlarges the range of applications that can be validated using Signal. Key-words: Signal, real-time languages, c...

In this report we present a significant extension of the quantified equation based algorithm class of piecewise regular algorithms. The main contributions of the following report are: (1) the class of piecewise regular algorithms is extended by allowing run-time dependent conditionals, (2) a mixed integer linear program is given to derive optimal schedules of the novel class we call dynamic piecewise regular algorithms, and (3) in order to achieve highest performance, we present a speculative scheduling approach. The results are applied to an illustrative example.

. In this paper we present affine transformations as an extension of the Signal language for the specification and validation of real-time systems. To each Signal program is associated a system of equations which specify synchronization constraints on clock variables. The Signal compiler resolves these equations and verifies if the control of a program is functionally safe. By means of the new transformations, affine relations can be defined between clocks and it gets necessary to enhance the compiler with facilities for the resolution of synchronization constraints on these clocks. We propose thus an extension of the compiler based essentially on a canonical form of the affine relations. 1 Introduction Real-time systems, and more generally reactive systems [1], are in continuous interaction with their environment. Therefore, they must respond in time to external stimuli. Moreover, real-time systems must be safe, thus one would wish to prove their correctness. Response time ...

In this paper, we introduce a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today’s hardware technology, may be implemented on a single chip (SoC – System on a Chip). Existing approaches for mapping computational-intensive algorithms to parallel architectures either consider the implementation in dedicated hardware or the implementation on a given supercomputer. Many intermediate solutions between these extremes are coming up ranging from finegrained FPGAs to coarse-grained processor arrays. For these architectures, we propose in this contribution a codesign approach in the sense of designing special purpose parallel processor architectures and efficient mapping tools simultaneously.