Compressing the instructions of an embedded program is important for cost-sensitive lowpower control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. We find that code compression with appropriate hardware optimizations does not have to incur much performance loss. Furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. Surprisingly, we find that a performance increase over native code is achievable in many situations. Keywords: Compression, CodePack, Code...

This work introduces a technique which applies a stack-based intermediate code, also called as bytecodes, to reduce the size of programs in an embedded system. A hardware interpreter known as the Translation Unit translates bytecodes into native codes before execution. Experiments show that a program written in bytecodes is smaller than one written in native codes by 16%-38%. Keyword: Code-size reduction, Code compression, Embedded system, Bytecode.

This work proposed an instruction set that achieved small executable codes for embedded applications. The aim of the design is to reduce the size of the executable code while maintaining the execution speed. Rather than applying instruction compression which required complex additional circuits, the approach taken in this work is to design the instruction set for the purpose of compact code. The result from a small set of benchmark illustrated that the static code size can be half of a conventional instruction set while the execution speed is maintained. Key-Words: Compact code, instruction compression, embedded processor.

In this paper, an efficient code size optimization instruction set architecture targeting embedded telecommunication applications is introduced. Nowadays, mixed 16-bit and 32bit size instruction set approaches are commonly used to achieve code size reduction while minimizing performance loss. They are usually designed with some restrictions such as reducing the number of accessible registers, mode switching, or special hardware logic handling. The approach starts with a common, basic RISC ISA [6] and a re-targetable high performance compiler. The Open64 compiler was chosen for its machine independent optimization so that once retargeted, the generated code will be of high performance quality. Once retargeted, we start our ISA compression design based on statistics collected from the code generated. By judicious selection from actual instructions generated, a high code compression rate is achieved without adding restrictions to the number of registers used and hardware implementation. Furthermore, this approach does not introduce any noticeable performance degradation due to the mixed 32/16-bit ISA compared to the full 32-bit ISA.