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High-Frequency Distortion Analysis of Analog Integrated Circuits
- IEEE Trans. Circuits Syst. II
, 1999
"... An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, ..."
Abstract
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An approach is presented for the analysis of the nonlinear behavior of analog integrated circuits. The approach is based on a variant of the Volterra series approach for frequencydomain analysis of weakly nonlinear circuits with one input port, such as amplifiers, and with more than one input port, such as analog mixers and multipliers. By coupling numerical results with symbolic results, both obtained with this method, insight into the nonlinear operation of analog integrated circuits can be gained. For accurate distortion computations, the accuracy of the transistor models is critical. A MOS transistor model is discussed that allows us to explain the measured fourth-order nonlinear behavior of a 1-GHz CMOS upconverter. Further, the method is illustrated with several examples, including the analysis of an operational amplifier up to its gain-bandwidth product. This example has also been verified experimentally. Index Terms---Analog integrated circuits, harmonic distortion, nonlinear ...
Parallel Model Valuation for Circuit Simulation on the PACE Multiprocessor
"... this paper. An element's submatrix contributes to more than one row in the matrix depending upon the element's connectivity in the circuit. These rows may be locally present in the processor on which the evaluation is done or they may have been assigned to other processors. In the latter case, the r ..."
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this paper. An element's submatrix contributes to more than one row in the matrix depending upon the element's connectivity in the circuit. These rows may be locally present in the processor on which the evaluation is done or they may have been assigned to other processors. In the latter case, the results of model evaluation are communicated over the interconnection network. If the matrix stamp is communicated then its value along with its address in the destination processor must be transmitted. The receiving processor will read the value and store it at the appropriate location in its data structure. In the following sections, we present a set of heuristics for assigning the circuit elements to the processors. 3.1 Partitioning of Circuit Elements for LOAD

