This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new approximate scheme to perform the delay calculations with stochastic delay values in linear time. The results are validated with Monte Carlo simulations. From a mathematical analysis some counter--intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst--case timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits for a given delay model. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 -- 14%. Furthermore, due to the mathematical properties of the delay...

We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid. In this paper we formulate the gate sizing problem for gate sizing for minimal power while removing glitches. We take into account both dynamic power dissipation as well as short-circuit power dissipation. To remove glitches we introduce additional constraints. We discuss the merits of the formulation and the problems encountered ...

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stochastic delay values. From a mathematical analysis some counter--intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst-- case timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 -- 14%. Furthermore, due to the mathematical properties of the delay calculations, the uncertainty in the delay of a circuit is usually much smaller than the uncertainty in t...

Gate sizing is used to scale the drive capability of CMOS-gates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear programming formulation can be solved by an interior point method. Solving this linear program takes considerable time and the accuracy typically required for gate sizing is not too demanding. A possibility for a speed-accuracy trade-off exists. We propose to use the primal-dual gap of an interior point method for linear programming as a measure of not only the achieved accuracy of the objective function, but also as a measure of the achieved accuracy of the sizing factors of individual gates. Terminating early once the desired accuracy is reached renders runtime improvements. Keywords--- logic synthesis, timing and power optimization, interior point methods I. Introduction Gate sizing i...

Gate sizing is used to increase the performance and/or decrease the area and/or power dissipation of CMOS circuits. There has been extensive work on gate sizing introducing several different methods, producing mixed results in solving speed, size of benchmark circuits and accuracy. These papers however rarely make comparisons between solving methods and usually only use small benchmarks. We introduce a sizable model for CMOS gates. Using this model we describe a gate sizing formulation for CMOS circuits. This model contains linear and some nonlinear equations. We solve the gate sizing formulation with three linear programming solvers for which we linearize the nonlinear equations. We also solve the gate sizing problem with a geometric and a general nonlinear programming solver. We present results for the five solvers for circuits up to a several thousand gates. We also discuss the advantages and disadvantages of each solver for the purpose of gate sizing.