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Concurrent Logic Restructuring and Placement for Timing Closure
 in Proc. IEEE International Conference on Computer Aided Design
, 1999
"... ABSTRACT: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of supercells along the critical paths and then generates the set of noninferior remapping solutions for each supercell. The best mapping and placement solu ..."
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Cited by 15 (0 self)
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ABSTRACT: In this paper, an algorithm for simultaneous logic restructuring and placement is presented. This algorithm first constructs a set of supercells along the critical paths and then generates the set of noninferior remapping solutions for each supercell. The best mapping and placement solutions for all supercells are obtained by solving a generalized geometric programming (GGP) problem. The process of identifying and optimizing the critical paths is iterated until timing closure is achieved. Experimental results on a set of MCNC benchmarks demonstrate the effectiveness of our algorithm. I.
Simultaneous Gate Sizing and Placement
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2000
"... In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and op ..."
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Cited by 13 (3 self)
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In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fanouts of the gates on the kmost critical paths; b) size down the immediate fanouts of the gates on the kmost critical paths; c) simultaneously reposition and resize the gates on the kmost critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1
Using Gate Sizing to Reduce Glitch Power
 in Proc. of the ProRISC Workshop on Circuits, Systems and Signal Processing, (Mierlo, The
, 1996
"... We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOSgates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a del ..."
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Cited by 12 (0 self)
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We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOSgates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid. In this paper we formulate the gate sizing problem for gate sizing for minimal power while removing glitches. We take into account both dynamic power dissipation as well as shortcircuit power dissipation. To remove glitches we introduce additional constraints. We discuss the merits of the formulation and the problems encountered ...
Computing the Entire Active Area / Power Consumption versus Delay Tradeoff Curve for Gate Sizing with a Piecewise Linear Simulator
, 1994
"... The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost ..."
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Cited by 5 (3 self)
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The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay tradeoff curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce tradeoff curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 twolevel examples are given. Keywords Logic Synthesis, Gate Sizing, Transistor Sizing, Low Power, Linear Programming, Circuit Simulation I. Introduction A. The gate sizing problem The ...
M.Pedram “Gate sizing with controlled Displacement
 in Proceedings of international symposium on physical design
"... Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively ident ..."
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Cited by 2 (1 self)
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Abstract In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a pathbased delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. All the operations are formulated and solved as mathematical programming problems by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches, which separate gate sizing from gate placement. 1
SpeedAccuracy Tradeoff in Gate Sizing
"... Gate sizing is used to scale the drive capability of CMOSgates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear ..."
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Gate sizing is used to scale the drive capability of CMOSgates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear programming formulation can be solved by an interior point method. Solving this linear program takes considerable time and the accuracy typically required for gate sizing is not too demanding. A possibility for a speedaccuracy tradeoff exists. We propose to use the primaldual gap of an interior point method for linear programming as a measure of not only the achieved accuracy of the objective function, but also as a measure of the achieved accuracy of the sizing factors of individual gates. Terminating early once the desired accuracy is reached renders runtime improvements. Keywords logic synthesis, timing and power optimization, interior point methods I. Introduction Gate sizing i...