We propose to size gates for minimum circuit power dissipation while balancing path delays in the circuit. Delay balancing using the filtering effect of CMOS-gates avoids superfluous transitions (glitches) resulting in power saving and increased circuit reliability. The transition densities in a delay balanced circuit are the same as the transition densities calculated with a zero delay model. Guaranteeing a transition density as calculated with a zero delay model makes logic decomposition and technology mapping for low power much easier and makes the much used zero delay model assumption in logic decomposition and technology mapping for low power more valid. In this paper we formulate the gate sizing problem for gate sizing for minimal power while removing glitches. We take into account both dynamic power dissipation as well as short-circuit power dissipation. To remove glitches we introduce additional constraints. We discuss the merits of the formulation and the problems encountered ...

In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing constraints in the circuit. To reduce the problem size and improve the solution convergence, we iteratively identify and optimize the kmost critical paths in the circuit and their neighboring cells. More precisely in each iteration, we perform three operations: a) reposition the immediate fan-outs of the gates on the k-most critical paths; b) size down the immediate fan-outs of the gates on the k-most critical paths; c) simultaneously reposition and resize the gates on the k-most critical paths. Each of these operations is formulated and solved as a mathematical program by using efficient solution techniques. Experimental results on a set of benchmark circuits demonstrate the effectiveness of our approach compared to the conventional approaches which separate gate sizing from gate placement. 1

The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay trade-off curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce trade-off curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 two-level examples are given. Keywords--- Logic Synthesis, Gate Sizing, Transistor Sizing, Low Power, Linear Programming, Circuit Simulation I. Introduction A. The gate sizing problem The ...

Gate sizing is used to scale the drive capability of CMOS-gates in order to improve the timing or to reduce the power dissipation of a logic circuit. Gate sizing can be formulated as a nonlinear optimization problem. This nonlinear optimization problem in turn can be linearized. The resulting linear programming formulation can be solved by an interior point method. Solving this linear program takes considerable time and the accuracy typically required for gate sizing is not too demanding. A possibility for a speed-accuracy trade-off exists. We propose to use the primal-dual gap of an interior point method for linear programming as a measure of not only the achieved accuracy of the objective function, but also as a measure of the achieved accuracy of the sizing factors of individual gates. Terminating early once the desired accuracy is reached renders runtime improvements. Keywords--- logic synthesis, timing and power optimization, interior point methods I. Introduction Gate sizing i...