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Systematic Serialisation of Array-Based Architectures
- Integration, the VLSI Journal
, 1993
"... This paper describes the use of Ruby, a language of functions and relations, to develop serialised implementations of array-based architectures. Our Ruby expressions contain parameters which can be varied to produce a wide range of designs with different space-time trade-offs. Such expressions can b ..."
Abstract
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Cited by 12 (6 self)
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This paper describes the use of Ruby, a language of functions and relations, to develop serialised implementations of array-based architectures. Our Ruby expressions contain parameters which can be varied to produce a wide range of designs with different space-time trade-offs. Such expressions can be obtained by applying correctness-preserving transformations to an initial simple description. This approach provides a unified treatment of serialisation schemes similar to LPGS (Locally Parallel Globally Sequential) and LSGP (Locally Sequential Globally Parallel) partitioning methods, and will be illustrated by the development of a variety of circuits for convolution. Keywords: Ruby, parametrised design, serialisation, correctness-preserving transformations, systolic arrays. 1 Introduction An attraction of array-based architectures, such as systolic networks, is the opportunity for customising them to cater for a specific application. One way of achieving customisation is to start from ...
Hardware Acceleration of Divide-and-Conquer Paradigms: a Case Study
- in Proc. IEEE Workshop on FPGAs for Custom Computing Machines, D.A. Buell and K.L. Pocek (eds.), IEEE Computer
, 1993
"... We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the "divide" and "merge" phases, while the "conquer" phase is handled by a purpose-built coprocessor. It is shown how transforma ..."
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Cited by 12 (4 self)
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We describe a method for speeding up divide-andconquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the "divide" and "merge" phases, while the "conquer" phase is handled by a purpose-built coprocessor. It is shown how transformation techniques from the Ruby language can be adopted in developing a family of systolic sorters, and how one of the resulting designs is prototyped in eight FPGAs on a PC coprocessor board known as CHS2x4 from Algotronix. The execution of the hardware unit is embedded in a sorting program, with the PC host merging the sorted sequences from the hardware sorter. The performance of this implementation is compared against various sorting algorithms on a number of PC systems. 1 Introduction It has long been recognised that the performance of a conventional processor can be speeded up many times if computationally-intensive operations are delegated to purpose-built hardware. Such hardware accele...

