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Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 17 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
Wire Sizing as a Convex Optimization Problem: Exploring the AreaDelay Tradeoff
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN
, 1996
"... ..."
Delay And Area Optimization For Discrete Gate Sizes Under DoubleSided Timing Constraints
 Proc. IEEE Custom Integrated Circuits Conf
, 1993
"... A threestep algorithm is presented for discrete gate sizing problem of delay#area optimization under doublesided timing constraints. The problem is #rst formulated as a linear program. The solution to the linear program is then mapped onto a permissible set. Using this permissible set, the gate si ..."
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Cited by 13 (2 self)
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A threestep algorithm is presented for discrete gate sizing problem of delay#area optimization under doublesided timing constraints. The problem is #rst formulated as a linear program. The solution to the linear program is then mapped onto a permissible set. Using this permissible set, the gate sizes are adjusted to satisfy the delaylower and upper bounds simultaneously.
HighPerformance CMOS System Design Using Wave Pipelining
, 1995
"... Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for ..."
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Cited by 6 (0 self)
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Wave pipelining, or maximum rate pipelining, is a circuit design technique that allows digital synchronous systems to be clocked at rates higher than can be achieved with conventional pipelining techniques. It relies on the predictable finite signal propagation delay through combinational logic for virtual data storage. Wave pipelining of combinational circuits has been shown to achieve clock rates 2 to 7times those possible for the same circuits with conventional pipelining. Conventional pipelined systems allow data to propagate from a register through the combinational network to another register prior to initiating the subsequent data transfer. Thus, the maximum operating frequency is determined by the maximum propagation delay through the longest pipeline stage. Wave pipelined systems apply the subsequent data to the network as soon as it can be guaranteed that it will not interfere with the current data wave. The maximum operating frequency of a wave pipeline is therefore determ...
Computing the Entire Active Area / Power Consumption versus Delay Tradeoff Curve for Gate Sizing with a Piecewise Linear Simulator
, 1994
"... The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost ..."
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Cited by 5 (3 self)
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The gate sizing problem is the problem of finding load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay tradeoff curve of a combinational logic circuit in an efficient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piecewise linear (circuit) simulator can do the job. It is shown that this setup is very efficient, and can produce tradeoff curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 twolevel examples are given. Keywords Logic Synthesis, Gate Sizing, Transistor Sizing, Low Power, Linear Programming, Circuit Simulation I. Introduction A. The gate sizing problem The ...
On Performance and Area Optimization of VLSI Systems Using Genetic Algorithms
 VLSI Design
, 1995
"... A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. ..."
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Cited by 3 (0 self)
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A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, nonRC based transistor delay model was used which resulted in a nonconvex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, nonconvex, nonlinear optimization problems than traditional calculusbased algorithms. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the ISCAS benchmark circuits. Key Words: Area and Performance optimization; Transistor Sizing; Genetic algorithms 1 Introduction The techniques for performance and area optimization of VLSI systems can be divi...
EFFICIENT COMPUTATION OF THE AREAPOWER CONSUMPTION VERSUS DELAY TRADEOFF CURVE FOR CIRCUIT CRITICAL PATH OPTIMIZATION
"... The paper introduces a novel methodology to obtain the entire arealpower consumption versus delay tradeoff curve for the critical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the trad ..."
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The paper introduces a novel methodology to obtain the entire arealpower consumption versus delay tradeoff curve for the critical path of a combinational logic circuit in a very efficient way. Compared to other proposed ways based on the optimization of the whole circuit for every point of the tradeoff curve, in this work only a subset of the boolean network representing the circuit is optimized each time. Performance comparison and results based on the MCNC'91 set of twolevel benchmark circuits are given. It is demonstrated that the proposed methodology produces tradeoff curves for large circuits of thousands of gates greatly reducing the computation complexity (measured in number of variables of an equivalent linear programming problem) by a factor up to 16 times. 1.
Timing Optimization By Gate Resizing And Critical Path Identification
 IEEE trans. On CAD of Integrated Circuits and Systems
, 1995
"... Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a majo ..."
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Due to the rapid progress in VLSI technology, the overall complexity of the chip has increased dramatically. There is a simultaneous need for more functions and higher speed in modern VLSI engineering. Therefore, using a minimum amount of extra hardware to meet timing requirements is becoming a major issue in VLSI design. Here, we propose an efficient method for timing optimization using gate resizing. To control the hardware overhead, a minimum (or as small as possible) number of gates are selected for resizing with the aid of a powerful benefit function. To guarantee the performance of timing optimization, a modified version of PODEM [1], called PODEM, ensures that each resized gate is located on at least one critical path. Thus, resizing a gate definitely reduces circuit delay. Simulation results demonstrate that our timing optimization method can efficiently reduce circuit delay with a limited amount of gate resizing. 1 1. Introduction In recent years, semiconductor technology h...
Freescale Semiconductor
"... Abstractâ€”Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suf ..."
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Abstractâ€”Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NPhard [1]. Several (suboptimal) gate sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms. We develop a method to generate benchmark circuits (called eyecharts) of arbitrary size along with a method to compute their optimal solutions using dynamic programming. We evaluate the suboptimalities of some popular gate sizing algorithms. Eyecharts help diagnose the weaknesses of existing gate sizing algorithms, enable systematic and quantitative comparison of sizing algorithms, and catalyze further gate sizing research. Our results show that common sizing methods (including commercial tools) can be suboptimal by as much as 54 % (Vtassignment), 46 % (gate sizing) and 49 % (gatelength biasing) for realistic libraries and circuit topologies.