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DDDFM9001: Derivation of a Verified Microprocessor
, 1994
"... Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experience in a formal fra ..."
Abstract

Cited by 21 (6 self)
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Derivation and verification represent alternate approaches to design. Derivation aims at deriving a "correct by construction" design while verification aims at constructing a post factum "proof of correctness" for a design. However, as researchers and engineers gain design experience in a formal framework, both approaches are emerging as interdependent facets of design. The thesis of this work is that alternate forms of formal reasoning must be integrated if formal methods are to support the natural analytical and generative reasoning that takes place in engineering practice. As a vehicle for this research, the DDD digital design derivation system was implemented to study formal hardware design in an algebraic framework. DDD is a firstorder transformation system which mechanizes a basic design algebra for synthesizing digital circuit descriptions from highlevel functional specifications. The system is a collection of correctness preserving transformations that promote a topdown desig...
A Practical Methodology for the Formal Verification of RISC Processors
, 1995
"... In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage leve ..."
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Cited by 9 (0 self)
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In this paper a practical methodology for formally verifying RISC cores is presented. This methodology is based on a hierarchical model of interpreters which reflects the abstraction levels used by a designer in the implementation of RISC cores, namely the architecture level, the pipeline stage level, the clock phase level and the hardware implementation. The use of this model allows us to successively prove the correctness between two neighbouring levels of abstractions, so that the verification process is simplified. The parallelism in the execution of the instructions, resulting from the pipelined architecture of RISCs is handled by splitting the proof into two independent steps. The first step shows that each architectural instruction is implemented correctly by the sequential execution of its pipeline stages. The second step shows that the instructions are correctly processed by the pipeline in that we prove that under certain constraints from the actual architecture, no conflic...
*BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
 IN FMCAD
, 1996
"... We address the problem of formally verifying arithmetic instructions of microprocessors implemented by microprograms that contain loops. We try to avoid theorem proving techniques using a new symbolic representation: Binary Moment Diagrams (*BMDs). In order to use *BMDs for verifying sequential circ ..."
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Cited by 9 (0 self)
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We address the problem of formally verifying arithmetic instructions of microprocessors implemented by microprograms that contain loops. We try to avoid theorem proving techniques using a new symbolic representation: Binary Moment Diagrams (*BMDs). In order to use *BMDs for verifying sequential circuits as well as microprograms, we extend this representation and define several bitvector level operators. This extension is then integrated into an automatic verification system. We illustrate the paper with examples and we discuss power and weakness of *BMDs.