Abstract—An active interference cancellation scheme is presented to mitigate interference between Bluetooth and wireless local area network (IEEE 802.11 b) radios operating in close proximity. This method is extensible to other mutually interfering radio devices. A reference signal correlated to the original interferer is used to generate a cancellation signal by means of amplitude and phase alignment, and filtration. The filter employed emulates the coupling channel responsible for interference. An implementation of this procedure in 0.18- m Si-complementary metal–oxide–semiconductor (CMOS) integrated-circuit (IC) technology is also presented. The circuits fabricated are tunable and are controlled by a closed-loop adaptive process including an error minimization method. The cancellation system designed achieves 15–30 dB of interference suppression for different cases. A total power of 14 mW is dissipated by the CMOS ICs designed. Index Terms—Active circuits, adaptive control, band-limited signals, interference suppression, phase shifters, spread-spectrum communication. I.

With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spectrum. Consequently, speed binning of the high performance VLSI chips is essential and it costs significant amount of test application time. Further, the knowledge of the actual delay in the critical path of the circuit enables efficient use of typical low power methodologies e.g., voltage scaling, adaptive body biasing etc. In this paper, we have proposed a novel on-chip, low overhead and process tolerant delay measurement circuit which can estimate the critical path delay in a single clock period. This has the advantage of efficient on-chip speed binning. Keywords: Speed binning, delay measurement hardware, process variation. I.

Abstract- To become truly ubiquitous, sensor network nodes must achieve ultra low power consumption. This paper proposes the Energy-per-Useful-Bit (EPUB) metric for evaluating and comparing sensor network physical layers. EPUB includes the energy consumption of both the transmitter and receiver, and amortizes the energy consumption during the synchronization preamble over the number of data bits in the packet. Using EPUB, we compare six existing sensor network PHYs. Next, we optimize the PHY according to EPUB. We conclude that the EPUB of sensor network PHYs can be reduced by increasing data rate, lowering carrier frequency, and using simple modulation schemes such as OOK to reduce synchronization overhead. I.

Energy-efficiency is imperative to enable the deployment of sensor networks with satisfactory lifetime. Conventional power management in radio communication primarily focuses independently on the physical layer, medium access control (MAC) or routing and approaches differ depending on the levels of abstraction. At the physical layer, the fundamental trade-off that exists between transmission rate and energy is exploited. This leads to the lazy scheduling approach, which consists of transmitting with the lowest power over the longest feasible duration. At MAC level, power reduction techniques tend to keep the transmission as short as possible to maximize the radio's power-off interval. Those two approaches seem conflicting and it is not clear which one is the most appropriate for a given network scenario. In this paper, we propose a transmission strategy that combines both techniques optimally. We present a cross-layer solution to determine the best transmission strategy taking into account the transceiver power consumption characteristics, the system load and the scenario constraints. Based on this approach, we derive a low complexity, on-line scheduling algorithm that can be used to optimally organize the forwarding of the sensed information from cluster heads to the data sink (uplink) in a hierarchical sensor network. Results, considering Coded Frequency Shift Keying (FSK) modulation, show that depending on the scenario, a 50% extra power reduction is achieved in a realistic uplink data gathering context, compared to the case where only transmission rate scaling or shutdown is considered.

Abstract — Low phase noise monolithic oscillators are in high demand in this age of wireless communications. Although LC oscillators generally have better phase noise performance, there is motivation to design ring oscillators with comparable phase noise compared to LC oscillators. The advantages of ring oscillators include significantly less die area and generally wider tuning range. Ring oscillator phase noise analysis and simulation, however, often ignore power supply noise which is a major and possibly dominant contributor of phase noise. This paper presents a method of determining a given oscillator’s sensitivity to both intrinsic and power supply noise sources and provides a means for comparing different oscillator architectures based on this information. I.

Abstract—Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable tradeoffs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulator’s amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifier’s gain to reject supply noise is effectively restored. Analysis shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised, and experimental results from a 90 nm SOI test chip confirm that with the same power consumption, the proposed regulator achieves at least 4 dB higher supply rejection than the previous regulator design. Furthermore, simulations show that if not for other supply rejection-limiting components in the PLL, the supply rejection improvement of the proposed regulator is greater than 15 dB. Index Terms—Phase-locked loops, power supply noise, regulators. I.

Abstract—This paper deals with the challenges in the design of millimeter-wave CMOS radios and describes circuit and architecture techniques that lead to compact, low-power transceivers. Candidate topologies for building blocks such as low-noise amplifiers, mixers, oscillators, and frequency dividers are presented. Also, a number of radio architectures that relax the generation, division, and distribution of the local oscillator signal are reviewed. Last, integration issues for transmit and receive paths and for multiple beamforming transceivers are addressed. Index Terms—Low-noise amplifiers, Miller divider, millimeter-wave circuits, mixers, oscillators, transceiver architectures, 60-GHz band. I.

Abstract—A comprehensive study of ultrahigh-speed currentmode logic (CML) buffers along with the design of novel regenerative CML latches will be illustrated. First, a new design procedure to systematically design a chain of tapered CML buffers is proposed. Next, two new high-speed regenerative latch circuits capable of operating at ultrahigh-speed datarates will be introduced. Experimental results show a higher performance for the new latch architectures compared to the conventional CML latch circuit at ultrahigh-frequencies. It is also shown, both through the experiments and by using efficient analytical models, why CML buffers are better than CMOS inverters in high-speed low-voltage applications. Index Terms—Broad-band circuits, current mode logic, device mismatch, enviromental noise, tapered buffers, ultrahigh-speed CMOS circuits. I.

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High-performance analog-to-digital converters, digital-to-analog converters, and fractional- frequency synthesizers based on delta--sigma (16) modulation---collectively referred to as data converters---have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.