There exists a huge market for application specific processors used within embedded systems. This market is driven by consumer requirements (e.g., new products, more functionality and flexibility, product digitalization, better performance-cost ratio, portability) and processor design capabilities (i.e., what can we offer). Being successful within this market requires a short time-to-market; this necessitates usage of automated design tools. These tools should not only assist in the quick generation of a specific processor, but also enable the designer to investigate quickly, and quantitatively, a large set of alternative solutions. Therefore, these tools should be based on a flexible and programmable processor template. In this paper we propose the usage of Transport Triggered Architectures (TTAs) for such a processor template. TTAs can be compared to VLIWs; both can exploit the compile-time available instruction level parallelism. However, TTAs are programmed differently. TTAs combi...

Transport triggered architectures (TTAs) form a new class of architectures which are programmed by specifying data transports between function units. As side effect of these data transports these function units perform operations. Making these data transports visible at the architectural level contributes to the flexibility and scalability of processors. Furthermore it enables several extra code scheduling optimizations. These properties make TTAs very suitable for being applied for embedded processors. In this article we discuss TTAs, and explain how to generate efficient code for these architectures. The compiler must exploit the available instruction level parallelism inside applications by scheduling as many useful data transports per cycle as the architecture permits. The flexibility and scalability of TTAs will be demonstrated by focusing on a particular algorithm, the minimum cost contour detection algorithm. This algorithm is e.g. used in medicine to perform real-time contour d...