Designing leading-edge systems (e.g., communications systems) requires knowledge about the technological limits. Jitter is the limiting effect in ADCs with a digitization bandwidth between 1 MHz and 1 GHz. The effect of aperture jitter and clock jitter have been investigated previously. However, some very important aspects are still missing, in particular investigations on the spectral distribution of the jitter induced error. This gap is filled by this paper.

This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 m heavily--doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.

Future wireless communications systems are expected to provide ever higher data rates. Still, devices have to be produced at reasonable cost in order to be affordable to customers. The widely known impairments -- "dirt effects" -- in analog RF tend to aggravate as we go for the large transmission bandwidths and high carrier frequencies that usually come with an increased data throughput.

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Abstract — In this paper, we build a novel well-proved model for describing the combined error due to clock jitter and quantization noise on the performance of bandpass sigma delta (Σ∆) analog to digital converters (ADCs). The clock jitter is modeled as a timing variation of the sampling process which follows the characteristic of the Wiener process. Computer simulations as well as theoretical calculations are performed and the two confirm each other. Results show that clock jitter severely degrades the system’s performance in terms of achievable signal to noise ratio (SNR). It is also shown that, when the clock jitter becomes more dominant compared to the quantization noise, increasing the oversampling ratio (OSR) and/or the order of Σ ∆ ADCs do not improve the performance significantly. Index Terms- Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.

Abstract—Clock jitter and its effects on signal-to-noise ratio (SNR) were widely investigated in the published literatures. However, most of the issues mainly focused on white-Gaussian-noise-only clock jitter, based on the scenario (assumption) of ideal interference-free clock circuit design which never existed in reality. This paper presents a realistic analog to digital converter (ADC) performance analysis model based on better realistic circuit noise conditions, particularly investigated on the clock jitter error with the combination of Gaussian noise and circuit noise (interference). An analytical expression for the A/D conversion with such combined clock jitter error is developed. The computer simulations are presented, which showed excellent agreement with the developed expression. Also, a real experiment is carried out to bring forth a comprehensive evaluation in A/D system design. Keywords—analog-to-digital converter, clock jitter, signal-to-noise ratio, circuit noise I.

Abstract — In this paper, we analyze the effect of clock jitter on the performance of OFDM-based systems applying digital IF architecture. A bandpass Σ ∆ ADC is used for the analog to digital conversion process. An accurate and realistic model of the clock jitter in bandpass Σ ∆ ADC is implemented. Results from this paper show that clock jitter severely degrades OFDM system performance by introducing both phase and waveform noise. It is shown that for the case of sampling at IF stage, the effect of waveform noise is quite small and negligible compared to the phase noise effect. Therefore, an estimation and compensation method based on the existing phase noise compensation method is proposed for alleviating the effect of clock jitter. Simulation results are presented, showing the significant performance gain of our proposed algorithm, providing a new and innovative way of dealing with the clock jitter problem of bandpass A/D conversion in OFDM systems. Index Terms- Sigma-delta modulators, analog-to-digital conversion, clock jitter, signal-to-noise ratio.