: The sum-product algorithm (belief/probability propagation) can be naturally mapped into analog transistor circuits. These circuits enable the construction of analog-VLSI decoders for turbo codes, low-density parity-check codes, and similar codes. Index Terms: Turbo codes, iterative decoding, factor graphs, belief propagation, analog circuits. The material in this paper was presented in part at the 1998 IEEE Int. Symp. on Information Theory, Cambridge, MA USA, August 16-21, 1998, and at several other conferences. This research was supported by the Swiss National Science Foundation under Grant 21-49619.96. 1 Now with Signal and Information Processing Lab (ISI), ETH Zentrum, CH-8092 Zrich, Switzerland. The work was performed while with Endora Tech AG, Basel. 2 Signal and Information Processing Lab (ISI), ETH Zentrum, CH-8092 Zrich, Switzerland. 3 Now with Globespan Semiconductor Inc., 100 Schulz Drive, Red Bank, NJ 07701. The work was performed while with ISI/ETH Zurich. 4 Endo...

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

Introduction In 1998, Hagenauer [6, 7] and Loeliger et al. [9] independently proposed to decode error correcting codes by analog electronic networks. In contrast to previous work on analog Viterbi decoders (e.g. Shakiba et al. [15] and several others before, see [10]), the work both by Hagenauer and by Loeliger et al. was inspired by "turbo"-style decoding of codes described by graphs [5, 16, 17]. Large gains, in terms of speed or power consumption, over digital implementations were envisaged. More complete accounts on these new analog decoders were given in [8] and [10, 11]. Since 1998, much e#ort has been spent towards turning these ideas into working chips. While only decoders of "toy" codes have so far been successfully manufactured, extensive simulations of such circuits have not revealed any fundamental problems. Some progress has also been made in analyzing the e#ects of transistor mismatch [12]. While much remains to be learned, this author feels confident that analog decoder

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Let us now check that S; T; and Y satisfy the conditions of