Introduction In 1998, Hagenauer [6, 7] and Loeliger et al. [9] independently proposed to decode error correcting codes by analog electronic networks. In contrast to previous work on analog Viterbi decoders (e.g. Shakiba et al. [15] and several others before, see [10]), the work both by Hagenauer and by Loeliger et al. was inspired by "turbo"-style decoding of codes described by graphs [5, 16, 17]. Large gains, in terms of speed or power consumption, over digital implementations were envisaged. More complete accounts on these new analog decoders were given in [8] and [10, 11]. Since 1998, much e#ort has been spent towards turning these ideas into working chips. While only decoders of "toy" codes have so far been successfully manufactured, extensive simulations of such circuits have not revealed any fundamental problems. Some progress has also been made in analyzing the e#ects of transistor mismatch [12]. While much remains to be learned, this author feels confident that analog decoder

Abstract—Increasing demand for high-speed inter-chip interconnects requires faster links that consume less power. Channel coding can be used to lower the required signal-to-noise ratio for a specific bit error rate in a channel. There are numerous codes that can be used to approach the theoretical Shannon limit, which is the maximum information transfer rate of a communication channel for a particular noise level. However, the complexity of these codes prohibits their use in high-speed inter-chip applications. A low-complexity signaling scheme is proposed here. This method can achieve 3–5-dB coding gain over uncoded four-level pulse amplitude modulation (PAM). The receiver for this signaling scheme along with a regular 4-PAM receiver was designed and implemented in a 0.18- m standard CMOS technology. Experimental results show that the receiver is functional up to 2.5 Gb/s. This was verified with a bit error rate tester (BERT) and we were able to achieve error free operation at 2.5-Gb/s channel transfer rate. The entire receiver for this scheme consumes 22 mW at 2.5 Gb/s and occupies an area of 0.2 mm2. Index Terms—Channel coding, chip-to-chip communication, four-level pulse amplitude modulation (4-PAM), high-speed,

Abstract—Two techniques, shield and repeater insertion, are simultaneously investigated. Based on resource optimization, the relationship among noise, power, and delay is investigated. Coupling noise as a function of power dissipation is shown to behave parabolically. Due to this parabolic behavior, the minimum noise can be established. The resulting design expressions are compared with SPICE simulations, exhibiting good agreement. A design case is compared with only shielding and only repeater insertion techniques, exhibiting enhanced performance for different resources. I.

Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum coupling noise under power, delay, and area constraints. Design expressions exhibiting parabolic noise behavior are compared with SPICE simulations. Due to the parabolic coupled noise behavior, the minimum noise is established. Good agreement between the analytic results and SPICE simulations is shown.

PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, prof. dr. H. Brinksma, volgens besluit van het College voor Promoties in het openbaar te verdedigen