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17
Reduced Power Dissipation Through Truncated Multiplication
 in IEEE Alessandro Volta Memorial Workshop on Low Power Design
, 1999
"... Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be signi ..."
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Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits. 1: Introduction Highspeed parallel multipliers are fundamental building blocks in digital signal processing systems [1]. In...
DigitSet Conversion: Generalization and Application
 IEEE Transactions on Computers
, 1994
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Parallel Saturating Fractional Arithmetic Units
 IN 9TH GREAT LAKES SYMPOSIUM ON VLSI
, 1999
"... This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of ..."
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Cited by 13 (6 self)
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This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition 1
A fast parallel squarer based on divideandconquer
 IEEE J. SolidState Circuits
, 1997
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R.W; “Integer multiplication with overflow detection or saturation
 Issue 7, July 2000 Page(s):681  691
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Combined Unsigned and Two's Complement Saturating Multipliers
, 2000
"... In many digital signal processing and multimedia applications, results that overflow are saturated to the most positive or most negative representable number. This paper presents efficient techniques for performing saturating nbit integer multiplication on unsigned and two's complement number ..."
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Cited by 2 (1 self)
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In many digital signal processing and multimedia applications, results that overflow are saturated to the most positive or most negative representable number. This paper presents efficient techniques for performing saturating nbit integer multiplication on unsigned and two's complement numbers. Unlike conventional techniques for saturating multiplication, which compute a 2nbit product and then examine the n most significant product bits to determine if overflow has occurred, the techniques presented in this paper compute only the (n + 1) least significant bits of the product. Specialized overflow detection units, which operate in parallel with the multiplier, determine if overflow has occurred and the product should be saturated. These techniques are applied to designs for saturating array multipliers that perform either unsigned or two's complement saturating integer multiplication, based on an input control signal. Compared to array multipliers that use conventional methods for sa...
HighSpeed and LowPower PID Structures for Embedded Applications
 Proceedings of the 21th edition of the International Workshop on Power and Timing Modeling, Optimization and Simulation PATMOS, LNCS 6951
"... Abstract. In embedded control applications, controlrate and energyconsumption are two critical design issues. This paper presents a series of highspeed and lowpower finitewordlength PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same con ..."
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Abstract. In embedded control applications, controlrate and energyconsumption are two critical design issues. This paper presents a series of highspeed and lowpower finitewordlength PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same conditions, savings of 431 % and 20 % are respectively obtained in terms of controlrate and dynamic power consumption. In addition, the new multiplication algorithm generates scalable PID structures that can be tailored to the desired performance and power budget. All PIDs are implemented at RTL level as technologyindependent reusable IPcores. They are reconfigurable according to two compiletime constants: setpoint wordlength and latency.
A High Speed and Low Power VLSI Multiplier Using a Redundant Binary Booth Encoding
"... This paper proposes a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of a redundant binary addition. The redundant binary representation is effective in speed, for it does not require carry propagation. The drawback is hardware increase due to a redundant b ..."
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This paper proposes a new high speed and low power multiplier that uses a new encoding scheme, taking advantage of a redundant binary addition. The redundant binary representation is effective in speed, for it does not require carry propagation. The drawback is hardware increase due to a redundant bit. In this paper, we introduce a novel redundant binary Booth encoding scheme to eliminate the hardware overhead. Experimental results show that our multiplier exhibits the practical interest in highspeed and lower power designs.
An Efficient 3bitscan Multiplier without Overlappong Bits, and its 64X64 Bit Implementation
 In Proceedings of 7th Asia and South Pacific Design Automation Conference
, 2002
"... In this paper, we present an efficient 3bitscan multiplier without overlapping bits which has good powerdelayarea tradeoffs. Generation of partial product terms in this multiplier is performed in parallel with the multiplication operation. Parallel partial product generation results in a multip ..."
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In this paper, we present an efficient 3bitscan multiplier without overlapping bits which has good powerdelayarea tradeoffs. Generation of partial product terms in this multiplier is performed in parallel with the multiplication operation. Parallel partial product generation results in a multiplier which is faster than conventional sequential multipliers. The architecture of the 3bitscan multiplier without overlapping bits is therefore suitable for synchronous sequential multipliers which are required to operate at low power and at relatively high speed for their area. 1
A New Recursive Multibit Recoding Algorithm for HighSpeed and LowPower Multiplier
 ISSN 15461998, American Scientific Publishers (ASP
, 2012
"... Abstract—In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general spacetime partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (n/r), but also eliminates the need of precomputi ..."
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Abstract—In this paper, a new recursive multibit recoding multiplication algorithm is introduced. It provides a general spacetime partitioning of the multiplication problem that not only enables a drastic reduction of the number of partial products (n/r), but also eliminates the need of precomputing odd multiples of the multiplicand in higher radix (ß≥8) multiplication. Based on a mathematical proof that any higher radix ß=2 r can be recursively derived from a combination of two or a number of lower radices, a series of generalized radix ß=2 r multipliers are generated by means of primary radices: 2 1, 2 2, 2 5, and 2 8. A variety of higherradix (2 3 2 32) two’s complement 64x64 bit serial/parallel multipliers are implemented on Virtex6 FPGA and characterized in terms of multiplytime, energy consumption per multiplyoperation, and area occupation for r value varying from 2 to 64. Compared to reference algorithm, savings of 8%, 52%, 63% are respectively obtained in terms of speed, power, and area. In addition, a new lowpower and highlyflexible radix 2 r adapted technique for a multiprecision multiplication is presented.