Abstract—We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate–and–fire (I&F) neurons, adaptive synapses with spike–timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the “address–event representation ” (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron’s response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real–time complex spike–based learning algorithms. Index Terms—Address–event representation (AER), analog VLSI, integrate-and-fire (I&F) neurons, neuromorphic circuits, spike-based learning, spike-timing dependent plasticity (STDP). I.

The growing interest in pulse–based neural networks is encouraging the development of hardware implementations of massively parallel, distributed networks of Integrate–and– Fire (I&F) neurons. We have developed a mixed–mode (analog/digital) VLSI device that comprises a reconfigurable network of I&F neurons and adaptive synapses. The synapses receive input spikes and the neurons transmit output spikes (events) using an asynchronous Address–Event Representation (AER). In this paper we describe the network architecture, present experimental data demonstrating the characteristics of the single elements on the chip, and show that a competitive network configuration has Winner–Take–All (WTA) behavior and produces spike synchronization. 1.