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Architectural Synthesis of Timed Asynchronous Systems
 In Proc. International Conf. Computer Design (ICCD
, 1999
"... This paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponenti ..."
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Cited by 11 (1 self)
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This paper describes a new method for architectural synthesis of timed asynchronous systems. Due to the variable delays associated with asynchronous resources, implicit schedules are created by the addition of supplementary constraints between resources. Since the number of schedules grows exponentially with respect to the size of the given data ow graph, pruning techniques are introduced which dramatically improve runtime without signicantly aecting the quality of the results. Using a combination of data and resource constraints, as well as an analysis of bounded delay information, our method determines the minimum number of resources and registers needed to implement a given schedule. Results are demonstrated using some highlevel synthesis benchmark circuits and an industrial example. 1. Introduction Architecturallevel synthesis is the process of taking an abstract behavioral model of a desired circuit and rening it to an optimal macroscopic structure. Issues such as latency, ...
Automatic Synthesis of Transport Triggered Processors
 In First Annual Conf. of ASCI
, 1995
"... A designer can chose from several options when mapping an application into a combination of hardware and software. Usage of an ASIP offers the advantage of a large design freedom, allowing optimal tuning of performance and costs. However there are two major problems related to the design of ASIPs: 1 ..."
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Cited by 8 (4 self)
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A designer can chose from several options when mapping an application into a combination of hardware and software. Usage of an ASIP offers the advantage of a large design freedom, allowing optimal tuning of performance and costs. However there are two major problems related to the design of ASIPs: 1) the design trajectory is long, and 2) it is impossible to do a quantitative search of the whole design space. The alleviate these problems we propose a design trajectory based on a templated, transport triggered architecture. Using a restricted, but still very large, design space we are able to automate the design trajectory based on a quantitative analysis of many design points. This paper presents this design method and shows its results when the method is applied to two benchmarks. Keywords: CoSynthesis, Design space exploration, ASIP design, Transport triggering. 1 Introduction Designing ASICs based on templated application specific instruction set processors (ASIPs) is an attractive...
Circuit Optimization via Adjoint Lagrangians
 IEEE INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 1997
"... The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable paramete ..."
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Cited by 6 (3 self)
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The circuit tuning problem is best approached by means of gradientbased nonlinear optimization algorithms. For large circuits, gradient computation can be the bottleneck in the optimization procedure. Traditionally, when the number of measurements is large relative to the number of tunable parameters, the direct method [2] is used to repeatedly solve the associated sensitivity circuit to obtain all the necessary gradients. Likewise, when the parameters outnumber the measurements, the adjoint method [1] is employed to solve the adjoint circuit repeatedly for each measurement to compute the sensitivities. In this paper, we propose the adjoint Lagrangian method, which computes all the gradients necessary for augmentedLagrangianbased optimization in a single adjoint analysis. After the nominal simulation of the circuit has been carried out, the gradients of the merit function are expressed as the gradients of a weighted sum of circuit measurements. The weights are dependent on the nominal solution and on optimizer quantities such as Lagrange multipliers. By suitably choosing the excitations of the adjoint circuit, the gradients of the merit function are computed via a single adjoint analysis, irrespective of the number of measurements and the number of parameters of the optimization. This procedure requires close integration between the nonlinear optimization software and the circuit simulation program. The adjoint
Response Surface Models using function values and gradient information, with application to the design of an electromagnetic device
"...  Response Surface Models (RSMs) can be used to model expensive simulations or real measurements [1]. A RSM is constructed by simulating solutions at systematic points in a design space and tting a model to them. The RSM is then employed in subsequent calculations (for instance in optimisation) eect ..."
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Cited by 3 (2 self)
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 Response Surface Models (RSMs) can be used to model expensive simulations or real measurements [1]. A RSM is constructed by simulating solutions at systematic points in a design space and tting a model to them. The RSM is then employed in subsequent calculations (for instance in optimisation) eectively replacing the original expensive simulator  this leads to considerable savings in time and money. We present a novel technique which uses the gradient of a function as well as the function itself to construct the RSM. Such an approach is possible because for many types of simulations, gradient information is simple and cheap to obtain. The design of an electromagentic speaker assembly is used to illustrate the new approach. The Finite Element Method (FEM), on which the simulation is based can provide gradient information at little extra cost and hence the benets of using gradient information are considerable, being especially marked in higherdimensional spaces. I. Introduction T...
ArchitecturalLevel Synthesis Of Asynchronous Systems
, 1998
"... Asynchronous circuit design has the potential to produce circuits superior to those of synchronous circuit design. Current synchronous methods of architecturallevel synthesis do not exploit properties inherent to asynchronous circuits. This research describes potential optimizations and techniques ..."
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Cited by 3 (1 self)
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Asynchronous circuit design has the potential to produce circuits superior to those of synchronous circuit design. Current synchronous methods of architecturallevel synthesis do not exploit properties inherent to asynchronous circuits. This research describes potential optimizations and techniques that can be applied to the architecturallevel design of asynchronous systems. The proposed methods take advantage of asynchronous circuit properties such as datadependent delays, modularity, and composiblity. The optimization problems of scheduling and allocation are studied. For scheduling, some counterintuitive properties of delays in a system are shown. The design space is studied and several filters to reduce the size of the design space are proposed. To evaluate and test these ideas the CAD tool Mercury was developed and is described in detail. Mercury is unique in that it can take an abstract model of a design, in this case a data flow graph, and from that generate both an optimal s...
Constraints Space Management for the Layout of Analog IC's
 In Proc. Design Automation & Test in Europe
, 1998
"... An automated technique to narrow down the number of constraints in analog layout is described. The set of most important layout constraints is determined, discarding unnecessary constraints. The method is based on principal component analysis of the sensitivity matrix. Experimental results suggest t ..."
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Cited by 2 (1 self)
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An automated technique to narrow down the number of constraints in analog layout is described. The set of most important layout constraints is determined, discarding unnecessary constraints. The method is based on principal component analysis of the sensitivity matrix. Experimental results suggest the effectiveness of the method with respect to parasitic estimation and to the error margin. The results are compared with human designers' art in handcrafted constraints confinement. 1. Introduction High performance analog IC layout is the more laborious part of an IC design task. The main problems in today's deepsubmicron layout design are stray parasitics, signal integrity and crosstalk, which forces the designers to adopt special strategies for stateoftheart analog design. Analog and mixed design are facing the problems of lowpower lowvoltage requirements, which further complicate analog layout. This generally results in costly iterations between behavioral and physical design, i...
System synthesis for polymorphous computing architectures
"... In general, polymorphous computing architectures are architectures that can be dynamically customized to various applications. This report is concerned with metrics, formulations, and algorithms for systematically synthesizing architectural configurations and software for such architectures, particu ..."
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Cited by 1 (1 self)
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In general, polymorphous computing architectures are architectures that can be dynamically customized to various applications. This report is concerned with metrics, formulations, and algorithms for systematically synthesizing architectural configurations and software for such architectures, particularly in the domain of digital signal processing (DSP). In polymorphous system synthesis for DSP, one central aspect is managing tradeoffs between latency and throughput, which are critical metrics for DSP applications. In Sections 14 of the report, we develop a model for latency that is more appropriate than conventional models of latency for DSP system synthesis, and that takes into account central issues related to transientstate time, and we develop precise relationships between latency and throughput using this framework. Schedule postprocessing strategies based on simulation and retiming that reduce the latency and transient for a given throughput constraint are then presented, and their efficacy is substantiated with experimental results on a number of practical DSP benchmarks. Also, a streamlined approach based on a graphtheoretic framework is suggested that leads to much faster execution of the proposed schedule postprocessing techniques. Sections 56 of the report then deal with the problem of efficient mapping of an application with stochastic execution times to a polymorphous computing architecture in accordance with the timevarying performance requirements for several metrics, which may include even nontrivial metrics such as the coupled latency/ throughput metrics that are addressed earlier in the report. A comprehensive model for system synthesis in this context is developed; results are developed on the complexity of system synthesis under this model; and preliminary algorithms that address the synthesis problem are presented, and evaluated experimentally. 1 1.
METHODS FOR CALCULATING FRÉCHET DERIVATIVES AND SENSITIVITIES FOR THE NONLINEAR INVERSE PROBLEM:
"... ..."
PERFORMANCE ANALYSIS OF POLYMORPHOUS COMPUTING ARCHITECTURES
, 2001
"... In general, polymorphous computing architectures are architectures that can be dynamically customized to various applications. This thesis is concerned with metrics, formulations, and algorithms for systematically synthesizing architectural configurations and software for such architectures, particu ..."
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In general, polymorphous computing architectures are architectures that can be dynamically customized to various applications. This thesis is concerned with metrics, formulations, and algorithms for systematically synthesizing architectural configurations and software for such architectures, particularly in the domain of digital signal processing (DSP). In polymorphous system synthesis for DSP, one central aspect is managing tradeoffs between latency and throughput, which are critical metrics for DSP applications. In Chapters 14 of the thesis, we develop a model for latency that is more appropriate than conventional models of latency for DSP system synthesis, and that takes into account central issues related to transientstate time, and we develop precise relationships between latency and throughput using this framework. Schedule postprocessing strategies based on simulation and retiming that reduce the latency and transient for a given throughput constraint are then presented, along with an approach based on graphtheoretic framework to streamline them, and their efficacy is substantiated with experimental results. Chapters 56 of the thesis then deal with the problem of efficient mapping of
Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup
"... Abstract — This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a ..."
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Abstract — This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. 1.