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14
Spectral shaping of circuits errors in digitaltoanalog converters
 IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process
, 1997
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Adaptive digital correction of analog errors in MASH ADCs. I. Offline and blind online calibration
 IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, 2000
"... Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect ..."
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Abstract—Cascaded delta–sigma (MASH) modulators for higher order oversampled analogtodigital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta–sigma stages. This first part of the paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents algorithms and architectures for digital correction of such analog imperfections, as well as gain and spectral distortion in the signal transfer function. Digital correction is implemented by linear finiteimpulse response (FIR) filters, of which the coefficients are determined through adaptive offline or online calibration. Of particular interest is an online “blind ” calibration technique, that uses no reference and operates directly on the digital output during conversion, with the only requirement on the unknown input signal that its spectrum be bandlimited. Behavioral simulations on dualquantization oversampled converters demonstrate nearperfect adaptive correction and significant improvements in signaltoquantizationnoise performance over the uncalibrated case, using as few as 5 FIR coefficients. An alternative online adaptation technique using test signal injection and experimental results from silicon are presented in the second part, in a companion paper [1]. Index Terms—Adaptation, analogtodigital conversion, blind
An approach to tackle quantization noise folding in doublesampling 61 modulation A/D converters
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is ..."
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Cited by 6 (4 self)
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Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is twice the masterclock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an indepth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of singlebit and multibit modulators are discussed. Index Terms—Analogtodigital conversion, doublesampling, spectral shaping.
An Overview of SigmaDelta Converters: How a 1bit ADC achieves more than 16bit resolution
, 1996
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MINLP Based Topology Synthesis for DeltaSigma Modulators Optimized for
 Signal Path Complexity, Sensitivity and Power Consumption”, Proc. DATE, 2005
"... This paper proposes a novel architecture synthesis algorithm for singleloop singlebit ∆Σ modulators. We defined a generic modulator architecture, derived its transfer function (TF), and used the TF in a MINLP formulation to generate optimal topologies for a variety of requirements. Experiments sho ..."
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Cited by 1 (1 self)
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This paper proposes a novel architecture synthesis algorithm for singleloop singlebit ∆Σ modulators. We defined a generic modulator architecture, derived its transfer function (TF), and used the TF in a MINLP formulation to generate optimal topologies for a variety of requirements. Experiments show the superiority of synthesized topologies as compared to traditional solutions. 1.
Analysis and Design of MultipleBit HighOrder \Sigma\Delta Modulator
 566 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 9, SEPTEMBER 2003 [13
, 1997
"... The highorder \Sigma\Delta modulator is an appropriate approach for highbandwidth, highresolution A/D conversion. However, nonideal effects such as the finite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance ..."
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The highorder \Sigma\Delta modulator is an appropriate approach for highbandwidth, highresolution A/D conversion. However, nonideal effects such as the finite opamp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable nonideal effects, we explore several multiplebit schemes, based on our CIQE highorder \Sigma\Delta architecture, to remove the nonideal deterioration. Design rules of these multiplebit schemes are developed and verified by extensive simulations. I. Introduction The A/D converter is an important element for digitalsignal processing systems. The cruxes of an A/D converter are high resolution for precise representation of the original signal and high bandwidth for fast processing. Conventional A/D architectures, e.g., flash, 2step flash, and successive approximation, are not suitable for highresolution applications because of the need of nearideal analog component...
A 1.8V, lMS/s, 85dB SNR 2+2 Mash EA Modulator with +0.9V Reference Voltage
"... A 1.8V, IMS/s, 8SdB SNR 2+2 mash ZA modulator with 10.9V reference voltage is realized by using the swing reduction sirnchue. Tlns smcture limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and hgh speed operation is possible with even high reference ..."
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A 1.8V, IMS/s, 8SdB SNR 2+2 mash ZA modulator with 10.9V reference voltage is realized by using the swing reduction sirnchue. Tlns smcture limits the output swing of all the integrators within half the reference voltage. Thus, low voltage and hgh speed operation is possible with even high reference voltage without degrading the performance of the modulator. The circuit is fabricated in CMOS 0.35um process with chip size of 2.5X2,5m2.
COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY
, 2004
"... Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytic ..."
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Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discretetime and continuoustime integration in voltagemode and in currentmode. For high resolution, superiority of switchedcapacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution. Keywords: Analog–digital conversion; sigma–delta modulation; signaltonoise analysis; low voltage CMOS; switched capacitors; switched current. 1.
ON FIXEDORDER FILTER DESIGN FOR UNCERTAIN CASCADED 21 SIGMADELTA MODULATORS: A DILATED PLANT APPROACH
, 2011
"... Abstract. This paper presents a new method to design the digital lters for correcting uncertain 21 cascaded sigmadelta () modulators. The main contribution of this paper consists of two parts. First, we develop a new lter design method, based on H1 loop shaping technique, to deal with a certain we ..."
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Abstract. This paper presents a new method to design the digital lters for correcting uncertain 21 cascaded sigmadelta () modulators. The main contribution of this paper consists of two parts. First, we develop a new lter design method, based on H1 loop shaping technique, to deal with a certain weighted matching condition with polytopic uncertainties in parameters. The feature of the proposed method is to show the lter order can be independent of the weighting function and determined beforehand. Therefore, in contrast to the conventional H1 loop shaping design method, lowerorder lters can be obtained by using the proposed method. The second contribution is the application of the proposed method. For uncertain cascaded modulators, a loworder lter with the same order of the nominal lter is designed, which can efficiently reduce the H1 norm of the noise transfer function in the signal frequency band. Consequently, the signaltonoise ratio (SNR) performance is improved. We compare the proposed method with other existing designs and establish its efficacy.