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An Analog VLSI Chip for Estimating the Focus of Expansion
 In 1997 ISSCC Digest of Technical Papers
, 1996
"... For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying ima ..."
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Cited by 6 (1 self)
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For applications involving the control of moving vehicles, the recovery of relative motion between a camera and its environment is of high utility. This thesis describes the design and testing of a realtime analog vlsi chip which estimates the focus of expansion (foe) from measured timevarying images. Our approach assumes a camera moving through a fixed world with translational velocity; the foe is the projection of the translation vector onto the image plane. This location is the point towards which the camera is moving, and other points appear to be expanding outward from. By way of the camera imaging parameters, the location of the foe gives the direction of 3D translation. The algorithm we use for estimating the foe minimizes the sum of squares of the differences at every pixel between the observed time variation of brightness and the predicted variation given the assumed position of the foe. This minimization is not straightforward, because the relationship between the brightn...
A Parallel Structure for CMOS FourQuadrant Analog Multipliers and Its Application to a 2GHz RF Downconversion Mixer
 IEEE Journal of solid state circuits
, 1998
"... A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier ..."
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Cited by 2 (0 self)
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A parallel structure for a CMOS fourquadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a lowvoltage highperformance CMOS fourquadrant analog multiplier is designed and fabricated by 0.8m Nwell doublepoly doublemetal CMOS technology. Experimental results have shown that, under a single 1.2V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximumscale input 500mVPP at both multiplier inputs. The 03dB bandwidth is 2.2 MHz and the dc current is 2.3 mA. By using the proposed multiplier as a mixercore and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5m singlepolydoublemetal Nwell CMOS technology. The experimental results have shown that, under 3V supply voltage and 2dBm LO power, the mixer has 01dB conversion gain, 2....
A 1V, 1V_pp Input Range, FourQuadrant Analog Multiplier Using NeuronMOS Transistors
, 1999
"... Introduction Analog multi#)MT8K are i#e ortantbui#%RH) blocksi n manysi#708 processi#9 ci#si#9D such as modulati#) ci#a cui#at frequency translati#0 ci#anslat fuzzy controllers and neural networks. Inparti#%)M8H many multi#H)M8H arerequi#KD for development of fuzzy controllers. In the reali#R0%)M o ..."
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Cited by 1 (0 self)
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Introduction Analog multi#)MT8K are i#e ortantbui#%RH) blocksi n manysi#708 processi#9 ci#si#9D such as modulati#) ci#a cui#at frequency translati#0 ci#anslat fuzzy controllers and neural networks. Inparti#%)M8H many multi#H)M8H arerequi#KD for development of fuzzy controllers. In the reali#R0%)M of defuzzi#M808DH ci#fuzzi (locatedi# the last block of fuzzy controllers), the number of multi#H)M89 i# di#lti#H proporti#KT0 to the number of fuzzy rules [1]. When the productsum composi#)KH i# used as a fuzzy reasoni#D method, the number of multi#0)M8K strongly depends on not only the number of fuzzy rules but also the number of fuzzy vari#79D) [2]. Furthermore, the ci#) cui#) wi## a large i#rge range arerequi#77 because vari #r si#)8D from sensors are treatedi# the fuzzy controllers [1]. From the abovedi#978)MK9% i# i# determi#K9 that lowpower andwi#KTDD7)MKR07R) multi#H)MKR are requi #)8 for development of fuzzy controllerswi#l many fuzzy rules. In other words, the lowpower
A CMOS Analog Hopfield Net with Local Adaption and Storage of Weights
, 1994
"... Tha later years have seen a large interest in artificial neural networks (ANN). Mostly this is due to their computation paradigm, massive parallel... ..."
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Tha later years have seen a large interest in artificial neural networks (ANN). Mostly this is due to their computation paradigm, massive parallel...
TOPIC: A GILBERT CELL MIXER IN CMOS AND BJT TECHNOLOGY1
"... Abstract – This paper describes a doubly balanced Gilbert Cell mixer designed in BJT and CMOS technology to operate within 0 to 5 V. A 100 mv input signal was applied at both RF and LO port at different frequencies and their simulation curves were studied for a multiplier. The design done in BJT was ..."
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Abstract – This paper describes a doubly balanced Gilbert Cell mixer designed in BJT and CMOS technology to operate within 0 to 5 V. A 100 mv input signal was applied at both RF and LO port at different frequencies and their simulation curves were studied for a multiplier. The design done in BJT was taped out for fabrication and the chip on its return from foundry, was tested for its results. A comparison of theoretical and experimental results obtained after fabrication of the FourQuadrant Gilbert cell mixer in 2micron process is made. For CMOS process, Gilbert cell mixer was designed till the layout and was ready for handoff to the foundry. The chip was not fabricated in CMOS technology, but the output results were studied and compared in both BJT and CMOS technology. 1.
doi:10.3906/elk1001377
"... A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement t ..."
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A novel fourquadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region is presented. The drain current is proportional to the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to implement the quarter square identity by utilizing only six FGMOS transistors. The main features of this remarkably simple multiplier circuit configuration are the large input signal range equal to 100 % of the supply voltage, nonlinearity of 0.0081%, bandwidth of 1.4–1.5 Ghz and THD of maximum 2.67 % (while the inputs are at their maximum values). Key Words: FGMOS, four quadrant analog multiplier, railtorail, differential amplifier 1.