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New Techniques for Efficient Verification with Implicitly Conjoined BDDs
, 1994
"... In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit ..."
Abstract

Cited by 26 (9 self)
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In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable.
Formal Hardware Verification with BDDs: An Introduction
"... This paper is a brief introduction to the main paradigms for using BDDs in formal hardware verification. The paper addresses two audiences: for people doing theoretical BDD research, the paper gives a glimpse of the problems in the main application area, and ..."
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Cited by 24 (0 self)
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This paper is a brief introduction to the main paradigms for using BDDs in formal hardware verification. The paper addresses two audiences: for people doing theoretical BDD research, the paper gives a glimpse of the problems in the main application area, and
Safe BDD Minimization Using Don't Cares
 In Design Automation Conf
, 1997
"... In many computeraided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algorithms have been developed to reduce the size of BDDs. This paper presents heuristic algorithms that minimize the size of B ..."
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Cited by 22 (2 self)
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In many computeraided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algorithms have been developed to reduce the size of BDDs. This paper presents heuristic algorithms that minimize the size of BDDs representing incompletely specified functions by intelligently assigning don't cares to binary values. The traditional algorithm, restrict [8], is often effective in BDD minimization, but can increase the BDD size. We propose new algorithms based on restrict which are guaranteed never to increase the size of the BDD, thereby significantly reducing peak memory requirements. Experimental results show that our techniques typically yield significantly smaller BDDs than restrict. 1 Introduction The efficient representation and manipulation of Boolean functions is critical to many computeraided design applications including logic synthesis, formal verification, and testing. Binary decision ...
Simulationbased functional test generation for embedded processors
 IEEE Tran. Computers
, 2006
"... Abstract—Deterministic functional test pattern generation has been a longstanding open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key in developing a practical functional test pattern generation approach is to avoid the exponentia ..."
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Cited by 1 (1 self)
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Abstract—Deterministic functional test pattern generation has been a longstanding open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key in developing a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the design size. This work proposes a novel functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions: Boolean learning for random logic and arithmetic learning for datapath modules. We demonstrate the effectiveness and discuss the limitations of these techniques through experiments on benchmark circuits. Last, we validate the overall test generation methodology based on the OpenRISC 1200 microprocessor. Index Terms—Simulation, test generation, functional test, learning 1
• Propositional resolution
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
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XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)
Stålmarck’s Procedure 2.19 Reduced Ordered Binary Decision Diagrams (ROBDDs) 2.23 Sequential Circuits Verification 2.55 Relational Representation of FSMs 2.56 Relational Product of FSMs 2.60 Reachability Analysis on FSMs 2.62
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
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XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)
Stålmarck’s Procedure 2.19 Reduced Ordered Binary Decision Diagrams (ROBDDs) 2.23 Sequential Circuits Verification 2.55 Relational Representation of FSMs 2.56 Relational Product of FSMs 2.60 Reachability Analysis on FSMs 2.62 Equivalence Checking Tools 2.
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
Abstract
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XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)
Cadence Labs Cadence Design Systems, Inc.
"... Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as a ..."
Abstract
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Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable. I.
Stålmarck’s Procedure 2.19 Reduced Ordered Binary Decision Diagrams (ROBDDs) 2.23 Sequential Circuits Verification 2.55 Relational Representation of FSMs 2.56 Relational Product of FSMs 2.60 Reachability Analysis on FSMs 2.62
"... XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two ..."
Abstract
 Add to MetaCart
XNOR, and blocks implementing more complex logic (Boolean) functions. • No logical loops, i.e., topologically there may be loops, but they are not sensitizable under any (valid) input combination, even such loops may be prohibited / not produced by automated analysis / synthesis tools Goal Given two Boolean netlists, check if the corresponding outputs of the two circuits are equal for all possible inputs • Two circuits are equivalent iff the Boolean function representing the outputs of the networks are logically equivalent • Identify equivalence points and implications between the two circuits to simplify equivalence checking • Since a typical design proceeds by a series of local changes, in most cases there are many implications / equivalent subcircuits in the two circuits to be compared • Various tautology/satisfiability checking algorithms based on heuristics (problem is NPcomplete, but many work well on “real ” applications...) • In this course we consider three main combinational equivalence checking methods: Propositional resolution method (tautology/satisfiability checking) Stålmarck’s method (recent patented algorithm, very efficient and popular) ROBDDbased method (Boolean function converted into ROBDD’s representation)