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New Techniques for Efficient Verification with Implicitly Conjoined BDDs
, 1994
"... In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit ..."
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Cited by 26 (9 self)
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In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable.
Formal Hardware Verification with BDDs: An Introduction
"... This paper is a brief introduction to the main paradigms for using BDDs in formal hardware verification. The paper addresses two audiences: for people doing theoretical BDD research, the paper gives a glimpse of the problems in the main application area, and ..."
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Cited by 25 (0 self)
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This paper is a brief introduction to the main paradigms for using BDDs in formal hardware verification. The paper addresses two audiences: for people doing theoretical BDD research, the paper gives a glimpse of the problems in the main application area, and
Safe BDD Minimization Using Don't Cares
 In Design Automation Conf
, 1997
"... In many computeraided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algorithms have been developed to reduce the size of BDDs. This paper presents heuristic algorithms that minimize the size of B ..."
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Cited by 22 (2 self)
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In many computeraided design tools, binary decision diagrams (BDDs) are used to represent Boolean functions. To increase the efficiency and capability of these tools, many algorithms have been developed to reduce the size of BDDs. This paper presents heuristic algorithms that minimize the size of BDDs representing incompletely specified functions by intelligently assigning don't cares to binary values. The traditional algorithm, restrict [8], is often effective in BDD minimization, but can increase the BDD size. We propose new algorithms based on restrict which are guaranteed never to increase the size of the BDD, thereby significantly reducing peak memory requirements. Experimental results show that our techniques typically yield significantly smaller BDDs than restrict. 1 Introduction The efficient representation and manipulation of Boolean functions is critical to many computeraided design applications including logic synthesis, formal verification, and testing. Binary decision ...
Simulationbased Functional Test Generation for Embedded Processors
 IEEE Tran. on Computers
, 2006
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Multilevel logic optimization of very high complexity circuits
 Proceedings of EURODAC'94
, 1994
"... The traditional approaches for multilevel logic optimization involve representing Boolean functions in SumofProduct forms that are minimized and then factorized in multilevel expressions. We have investigated an alternative approach called graphic synthesis that is based on a set of Reduced and Or ..."
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Cited by 2 (1 self)
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The traditional approaches for multilevel logic optimization involve representing Boolean functions in SumofProduct forms that are minimized and then factorized in multilevel expressions. We have investigated an alternative approach called graphic synthesis that is based on a set of Reduced and Ordered BDDs, namely a multiROBDD for representing Boolean functions. This approach allows the optimization of very high complexity circuits that cannot be synthesized by classical algorithms without applying drastical restrictions. We propose an algorithm for generating a multilevel expression from a BDD and a procedure that optimizes a multiROBDD by exploiting Don’t Cares and by searching an input variable ordering for minimizing the final cost of a Boolean network in terms of number of literals. We present results over a range of very high complexity circuits (up to 5.000 gates). 1
Performance Driven Resynthesis by Exploiting RetimingInduced State Register Equivalence
, 1999
"... : This paper presents a retiming and resynthesis technique for cycletime minimization of sequential circuits circuits with feedbacks (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and log ..."
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Cited by 1 (0 self)
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: This paper presents a retiming and resynthesis technique for cycletime minimization of sequential circuits circuits with feedbacks (finite state machines). Operating on the delay critical paths of the circuit, we perform a set of controlled local retimings of registers across fanout stems and logic gates, followed by local node simplifications. We guide the retiming of registers across fanout stems to induce equivalence relations among them, which are exploited for subsequent logic simplification. Our technique is able to analyze correlation of logic across register boundaries during simplification. We strive to minimize the increase in number of registers without sacrificing the cycletime performance. The results demonstrate a favourable performance /area tradeoff when compared with optimally retimed circuits. I. INTRODUCTION Conventional sequential synthesis techniques apply a variety of heuristic transformations that target the optimization of the combinational logic component...
Highlevel Symbolic Construction Techniques for High Performance Sequential Synthesis
"... Abstract ⎯ Techniques for constructing synchronous sequential machines with associated data paths from an input format consisting of highlevel nondeterministic productions are described. These construction techniques rely on recent work in symbolic Boolean representation and manipulation to produc ..."
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Abstract ⎯ Techniques for constructing synchronous sequential machines with associated data paths from an input format consisting of highlevel nondeterministic productions are described. These construction techniques rely on recent work in symbolic Boolean representation and manipulation to produce an intermediate machine representation that is not impacted by state explosion. I.
Clairvoyant: A Synthesis System for ProductionBased Specification
"... This paper describes a new highlevel synthesis system based on the hierarchical ProductionBased Specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables and that the designer does not des ..."
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This paper describes a new highlevel synthesis system based on the hierarchical ProductionBased Specification (PBS). Advantages of this form of specification are that the designer does not describe the control flow in terms of explicit states or control variables and that the designer does not describe a particular form of implementation. The productionbased specification also separates the specification of the control aspects and dataflow aspects of the design. The control is implicitly described via the production hierarchy, while the dataflow is described explicitly in action computations. This approach is a hardware analog of popular software engineering techniques. The Clairvoyant system automatically constructs a
Cadence Labs Cadence Design Systems, Inc.
"... Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as a ..."
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Abstract — In previous work, Hu and Dill identified a common cause of BDDsize blowup in highlevel design verification and proposed the method of implicitly conjoined invariants to address the problem. That work, however, had some limitations: the user had to supply the property being verified as an implicit conjunction of BDDs, the heuristic used to decide which conjunctions to evaluate was rather simple, and the termination test, though fast and effective on a set of examples, was not proven to be always correct. In this work, we address those problems by proposing a new, more sophisticated heuristic to simplify and evaluate lists of implicitly conjoined BDDs and an exact termination test. We demonstrate on examples that these more complex heuristics are reasonably efficient as well as allowing verification of examples that were previously intractable. I.