Results 1  10
of
15
Spectral Shaping of Circuit Errors in DigitaltoAnalog Converters
, 1997
"... Recently, various multibit noiseshaping digitaltoanalog converters (DAC's) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC's have the potential to significantly increase the present p ..."
Abstract

Cited by 44 (19 self)
 Add to MetaCart
Recently, various multibit noiseshaping digitaltoanalog converters (DAC's) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC's have the potential to significantly increase the present precision limits of 16 data converters by eliminating the need for onebit quantization in deltasigma modulators. This paper extends the practicality of the noiseshaping DAC approach by presenting a general noiseshaping DAC architecture along with two specialcase configurations that achieve first and secondorder noiseshaping, respectively. The secondorder DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noisethe errors introduced by the analog circuitryare not known to the ...
A 3.3V SinglePoly CMOS Audio ADC DeltaSigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR
 IEEE J. SolidState Circuits
, 2000
"... This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33leve ..."
Abstract

Cited by 18 (13 self)
 Add to MetaCart
This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33level #ash ADC with digital commonmode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixedsignal ICs with high digital circuit content, singlepoly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of doublepoly capacitors, thickoxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
A cascaded sigmadelta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
 IEEE Journal of SolidState Circuits
, 1997
"... Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. ..."
Abstract

Cited by 13 (0 self)
 Add to MetaCart
Abstract — A lownoise multibit sigma–delta analogtodigital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient highresolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16b implementation of the architecture, fabricated in a 0.6"m CMOS process, cascades a secondorder 5b sigma–delta modulator with a fourstage 12b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clockboosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25MHz signal bandwidth and a total harmonic distortion (THD) of 098 dB with a 100kHz input signal. Index Terms—Analogdigital conversion, bootstrapped switch, digital filters, dynamic element matching, pipeline processing, sigma–delta modulation, switched capacitor circuits. I.
An Audio ADC DeltaSigma Modulator with 100dB Peak SINAD and 102dB DR Using a SecondOrder MismatchShaping DAC
 IEEE J. Solid State Circuits
, 2001
"... A secondorder audio analogtodigital converter (ADC) 16 modulator using a secondorder 33level treestructured mismatchshaping digitaltoanalog converter (DAC) is presented. Key logic simplifications in the design of the mismatch shaping DAC encoder are shown which yield the lowest complexit ..."
Abstract

Cited by 10 (4 self)
 Add to MetaCart
A secondorder audio analogtodigital converter (ADC) 16 modulator using a secondorder 33level treestructured mismatchshaping digitaltoanalog converter (DAC) is presented. Key logic simplifications in the design of the mismatch shaping DAC encoder are shown which yield the lowest complexity secondorder mismatchshaping DAC known to the authors. The phenomenon of signaldependent DAC noise modulation in mismatchshaping DACs is illustrated, and a modified secondorder inputlayer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3V 0.5 m singlepoly CMOS prototype are presented. All 12 prototype devices achieve better than 100dB signaltonoiseanddistortion and 102dB dynamic range over a 1020 kHz measurement bandwidth. Index Termsanalogdigital conversion, CMOS analog integrated circuits, deltasigma modulation, digitalanalog conversion, dynamic element matching, mixed analogdigital integrated circuits. I.
Simplified Logic for FirstOrder and SecondOrder MismatchShaping DigitaltoAnalog Converters
 AND GALTON: NECESSARY AND SUFFICIENT CONDITIONS FOR MISMATCH SHAPING 759
, 2001
"... Mismatchshaping digitaltoanalog converters (DACs) have become widely used in highperformance deltasigma data converters because they facilitate deltasigma modulators with multibit quantization. Relative to singlebit quantization, multibit quantization significantly relaxes the analog circuit ..."
Abstract

Cited by 8 (5 self)
 Add to MetaCart
Mismatchshaping digitaltoanalog converters (DACs) have become widely used in highperformance deltasigma data converters because they facilitate deltasigma modulators with multibit quantization. Relative to singlebit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in deltasigma analogtodigital converters the mismatchshaping logic is in the feedback path of the deltasigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatchshaping logic. This paper presents and analyzes several variations of the switching blocks within a treestructured mismatchshaping DAC that result in the most hardwareefficient firstorder and secondorder mismatch shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagationdelay reduction so as to tailor designs to specific applications.
Necessary and Sufficient Conditions for Mismatch Shaping in a General Class of Multibit Dacs
, 2002
"... Multibit digitaltoanalog converters (DACs) are often constructed by combining several 1bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element ..."
Abstract

Cited by 7 (4 self)
 Add to MetaCart
Multibit digitaltoanalog converters (DACs) are often constructed by combining several 1bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatchshaping DACs and have been used widely as enabling components in stateoftheart data converters. Several different mismatchshaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatchshaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatchshaping DACs and qualitatively compare their behavior.
DeltaSigma Data Conversion in Wireless Transceivers
, 2002
"... Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wirel ..."
Abstract

Cited by 4 (2 self)
 Add to MetaCart
Highperformance analogtodigital converters, digitaltoanalog converters, and fractional frequency synthesizers based on deltasigma (16) modulationcollectively referred to as data convertershave contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.
Segmented Dynamic Element Matching for HighResolution DigitaltoAnalog Conversion
"... Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require ..."
Abstract

Cited by 4 (4 self)
 Add to MetaCart
Abstract—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mismatches among nominally identical components from introducing nonlinear distortion. It has long been used as a performanceenabling technique in deltasigma data converters which require lowresolution but highlinearity DACs. More recently, segmented DEM architectures have made highresolution Nyquistrate DEM DACs practical. However, the previously published segmented DEM DAC designs have been ad hoc. Systematic techniques for synthesizing segmented DEM DACs and analyses of their design tradeoffs have not been published previously. This paper quantifies a fundamental power dissipation versus complexity tradeoff implied by segmentation and provides a systematic method of synthesizing segmented DEM DACs that are optimal in terms of the tradeoff. Index Terms—Digitaltoanalog conversion, dynamic element matching (DEM), segmentation. I.
Quadrature Mismatch Shaping for DigitaltoAnalog Converters
"... Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise i ..."
Abstract

Cited by 3 (0 self)
 Add to MetaCart
Abstract—Quadrature sigma–delta analogtodigital converters require a feedback path for both the I and the Q parts of the complex feedback signal. If two separate multibit feedback digitaltoanalog converters (DACs) are used, mismatch among the unit DAC elements leads to additional mismatch noise in the output spectrum as well as an I/Q imbalance. This paper proposes new quadrature bandpass (QBP) mismatch shaping techniques. In our approach, the I and Q DACs are merged into one complex DAC, which leads to nearperfect I/Q balance. To select the unit DAC elements of the complex multibit DAC, the wellknown butterfly shuffler and tree structure are generalized towards a complex structure, and necessary constraints for their correct functioning are derived. Next, a very efficient firstorder QBP shaper implementation is proposed. Finally, the newly presented complex structures are simulated to prove their effectiveness and are compared with each other with respect to performance. Index Terms—Butterfly shuffler, mismatch shaping, quadrature bandpass (QBP), treestructured, 61 analogtodigital converters (ADCs). I.
A tight signalband power bound on mismatch noise in a mismatch shaping digitaltoanalog converter
 IEEE Trans. Inf. Theory
, 2004
"... Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
Abstract—Many applications employ digitaltoanalog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signaltonoise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatchshaping DACs exploit builtin redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatchshaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatchshaping DAC: the dithered firstorder lowpass treestructured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dcfree sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signalband DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analogtodigital, data converters, dcfree sequences, delta–sigma (16), digitaltoanalog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.