Classical logic has so far been the logic of choice in formal hardware verification. This paper proposes the application of intuitionistic logic to the timing analysis of digital circuits. The intuitionistic setting serves two purposes. The model-theoretic properties are exploited to handle the second-order nature of bounded delays in a purely propositional setting without need to introduce explicit time and temporal operators. The proof theoretic properties are exploited to extract quantitative timing information and to reintroduce explicit time in a convenient and systematic way. We present a natural Kripke-style semantics for intuitionistic propositional logic, as a special case of a Kripke constraint model for Propositional Lax Logic [15], in which validity is validity up to stabilisation, and implication oe comes out as "boundedly gives rise to." We show that this semantics is equivalently characterised by a notion of realisability with stabilisation bounds as realisers...

ions (from branching and real time) DRAFT Peter Sewell The Computer Laboratory, University of Cambridge Cambridge CB2 3QG, UK Peter.Sewell@cl.cam.ac.uk September 5, 1996 Abstract Three simple models of synchronous hardware are given; using linear discrete, branching discrete and branching real time. A simple notion of abstraction is introduced, motivated by the need to ultimately view such models as scientific theories that make empirical predictions. It makes the significance of design rules explicit. Two abstractions from the branching discrete to the linear discrete model are given. They shed some light on the roles of consistency, deadlock and determinacy. The stronger of the two depends on a notion of dynamic type for processes which ensures deadlock freedom. A reasonably strong abstraction from the branching real to the branching discrete model is given. This depends on a finer notion of type which is a reasonably physically plausible formalisation of the timing properties of ...

. We develop within higher order logic (HOL) a general and exible method of abstraction and renement, which specically addresses the problem of handling constraints. The method is based on an interpretation of rst-order Lax Logic in HOL, which can be seen as a modal extension of deliverables. It provides a new technique for automating reasoning about behavioural constraints. We show how the method can be applied in several dierent tasks, for example to achieve a formal separation of the logical and timing aspects of hardware design, and to generate systematically timing constraints for a simple sequential device from a formal proof of its abstract behaviour. The method and all proofs in the paper have been implemented in Isabelle as a denitional extension of the HOL logic. We assume the reader is familiar with higher order logic but do not assume detailed knowledge of circuit design. 1