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Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM Computing Surveys
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 879 (11 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
BitLevel Analysis of an SRT Divider Circuit
 IN PROCEEDINGS OF THE 33RD DESIGN AUTOMATION CONFERENCE, PAGES 661665, LAS VEGAS, NV
, 1995
"... It is impractical to verify multiplier or divider circuits entirely at the bitlevel using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using ..."
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Cited by 23 (0 self)
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It is impractical to verify multiplier or divider circuits entirely at the bitlevel using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we show that Intel could haveused BDDs to detect erroneous lookup table entries in the Pentium(TM) floating point divider. Going beyond verification, we show that bitlevel analysis can be used to generate a correct version of the table.
Functional decomposition of mvl functions using multivalued decision diagrams
 Proc. ISMVL'97
, 1997
"... In this paper, the minimization of incompletely specified multivalued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multivalued logic. The representation, can then be decomposed into smaller blocks, re ..."
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Cited by 9 (3 self)
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In this paper, the minimization of incompletely specified multivalued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multivalued logic. The representation, can then be decomposed into smaller blocks, resulting in a reduced problem complexity. This gives induced descriptions through structuring, or feature extraction, of a learning problem. Our approach to the decomposition is based on expressing a multivalued function (learning problem) in terms of a Multivalued Decision Diagram that allows the use of Don’t Cares. The inclusion of Don’t Cares is the emphasis for this paper since multivalued benchmarks are characterized as having many Don’t Cares. 1.
Cube Diagram Bundles: A New Representation Of Strongly Unspecified MultipleValued Functions And Relations
 Proc. ISMVL'97
, 1997
"... Efficient function representation is very important for speed and memory requirements of multiplevalued decomposers. This paper presents a new representation of multiplevalued relations (functions in particular), called MultipleValued Cube Diagram Bundles (MVCDB). MVCDBs improve on Rough Partitio ..."
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Cited by 7 (6 self)
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Efficient function representation is very important for speed and memory requirements of multiplevalued decomposers. This paper presents a new representation of multiplevalued relations (functions in particular), called MultipleValued Cube Diagram Bundles (MVCDB). MVCDBs improve on Rough Partition representation by labeling their blocks with variable values and by representing blocks efficiently. The MVCDB representation is especially efficient for very strongly unspecified multiplevalued input, multiplevalued output functions and relations, typical for Machine Learning applications. 1 I. Introduction. Multiplevalued functions and relations that include very many don't cares are becoming increasingly important in several areas of applications such as Machine Learning and Knowledge Discovery [16] and also in combinational and sequential circuit design. It is important to have an efficient representation for such relations. For instance, the successes of many binary decomposers d...
Incremental Methods for Formal Verification and Logic Synthesis
, 1996
"... Incremental Methods for Formal Verification and Logic Synthesis by Gitanjali Meher Swamy Doctor of Philosophy in EngineeringElectrical Engineering and Computer Sciences University of California, Berkeley Professor Robert K. Brayton, Chair IC design is an iterative process; the initial specification ..."
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Cited by 5 (0 self)
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Incremental Methods for Formal Verification and Logic Synthesis by Gitanjali Meher Swamy Doctor of Philosophy in EngineeringElectrical Engineering and Computer Sciences University of California, Berkeley Professor Robert K. Brayton, Chair IC design is an iterative process; the initial specification of a design is rarely complete and correct. The designer begins with a preliminary and usually incorrect sketch (possibly from a previous generation design), and iteratively refines and corrects it. Usually, refinements are small, and there is much common information between successive design iterations. The current genre of CAD tools do not take into account this iterative nature of design. For each change made to the design, the design is reverified and reoptimized without taking advantage of information from previous iterations. This leads to inefficient performance. In this thesis, we propose the paradigm of incremental algorithms for CAD. Incremental algorithms use information from a...
Multiple Boolean Relations
 in Workshop Notes of the Intl. Workshop on Logic Synthesis, (Tahoe City, CA
, 1993
"... Flexibility in selecting the Boolean functions to implement a digital circuit has various forms which have been studied in the literature such as don't care conditions, Boolean relations, and synchronous recurrence equations. Each of these represents a particular degree of flexibility that may be gi ..."
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Cited by 5 (3 self)
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Flexibility in selecting the Boolean functions to implement a digital circuit has various forms which have been studied in the literature such as don't care conditions, Boolean relations, and synchronous recurrence equations. Each of these represents a particular degree of flexibility that may be given in the description, inherent in the current representation, or derived from the surrounding environment. This flexibility is used to find an optimal implementation. In this paper, we propose a Multiple Boolean Relation (MBR) as a model that encompasses all degrees of freedom in choosing a set of Boolean functions to implement. This formulation unifies some of the recent work in logic synthesis, which has introduced new types of flexibility. We give examples of synthesis problems in which Multiple Boolean Relations arise and are the only model that represents all the flexibility available. We offer algorithms for obtaining an optimal solution to an MBR. 1 Introduction Optimization of Boo...
Sequential Circuit Synthesis at the Gate Level
, 1993
"... Sequential Circuit Synthesis at the Gate Level by Ellen Marie Sentovich Doctor of Philosophy in Electrical Engineering and Computer Sciences University of California at Berkeley Professor Robert K. Brayton, Chair Sequential circuit synthesis is the process of automatically generating an optimal impl ..."
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Cited by 3 (0 self)
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Sequential Circuit Synthesis at the Gate Level by Ellen Marie Sentovich Doctor of Philosophy in Electrical Engineering and Computer Sciences University of California at Berkeley Professor Robert K. Brayton, Chair Sequential circuit synthesis is the process of automatically generating an optimal implementation of a sequential circuit given a highlevel or gatelevel description. Optimization of a sequential circuit design may be performed at either the state transition graph level or the gate level. The published work to date has favored the state transition graph level because it allows one to reason easily about input/output sequences; however, the impact of optimization at this level is hard to quantify. The gatelevel view is important for several reasons: it provides a direct measure of the quality of the final implementation; all sequential designs must eventually be implemented at the gate level; given a gatelevel description it is usually computationally impractical to extract ...
Synthesis of controllers from Interval Temporal Logic specification
 International Workshop on Logic Synthesis
, 1993
"... ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 4. Make product 3. Presented synthesis method Sequential circuits 5. Logic synthesis State machines Figure 3: Flow of Our Redesign Method can vary according to ..."
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Cited by 1 (0 self)
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ed state machines Deterministic state machines 1. State machine extraction (e.g. stg_extract) 2. Eliminate conditions New constraints in ITL 4. Make product 3. Presented synthesis method Sequential circuits 5. Logic synthesis State machines Figure 3: Flow of Our Redesign Method can vary according to the variant of more(Q). So the number of generated formulas is less than the number of products of variants for more(P ) and more(Q). Since the tableau expansion generates a finite number of binary subterm diagram nodes, it generates only a finite binary subterm diagrams. When we expand all binary subterm diagrams, the expansion completes. 4 A Redesign Method for Sequential Circuits We can simply use the method which generates state machine representation from any ITL formulas as a procedure to synthesize state machines and hence sequential circuits from ITL formulas. However, we cannot handle very complex ITL formulas within a reasonable time, since the expansion time grows exponentially...
A recursive paradigm to solve Boolean relations
 Proc. DAC ’04
"... A recursive algorithm for solving Boolean relations is presented. It provides several features: wide exploration of solutions, parametrizable cost function and efficiency. The experimental results show the applicability of the method and tangible improvements with regard to previous heuristic approa ..."
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Cited by 1 (0 self)
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A recursive algorithm for solving Boolean relations is presented. It provides several features: wide exploration of solutions, parametrizable cost function and efficiency. The experimental results show the applicability of the method and tangible improvements with regard to previous heuristic approaches.
Asynchronous Multipliers with VariableDelay Counters
, 2001
"... Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are avalaible, it still represents one of the major bottlenecks of many digital systems that require intensive and fast computations. This paper presents a novel design approach based on ..."
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Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are avalaible, it still represents one of the major bottlenecks of many digital systems that require intensive and fast computations. This paper presents a novel design approach based on the wellknown Baugh and Wooley algorithm, particularly appealing for asynchronous implementations and that may be easily mapped into a VLSI circuit. This technique has been applied to the design of a highspeed variabledelay multiplier that resulted to be faster than other synchronous and asynchronous implementations. 1