A design methodology is presented to optimize application specific instruction set processors (ASIPs) with respect to performance and power. The methodology uses semi-custom design with incremental datapath and instruction set enhancements of a conventional, unoptimized architecture. ICORE, a low-power ASIP for DVB-T acquisition and tracking algorithms, demonstrates the huge potential concerning power savings of these optimizations.

Application specific instruction set processors (ASIPs) can be optimized both for speed and power taking advantage of the flexibility of a synthesized semi-custom implementation. The current case study evaluates the effect of datapath and instruction set optimization using two examples from terrestrial digital video broadcasting (DVB-T) acquisition and tracking algorithms.

Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of microns. However, the physical scale of MEMS devices can make controlling them computationally challenging because the time constants involved are often several orders of magnitude faster than macro-scale devices and because they often require very low power operation. In this paper we begin an examination of the suitability of two different digital signal processors to the high-speed closed loop control problems faced by this new and growing domain. Working with domain experts in the area we characterize the classic tight feedback control loops required by these next generation MEMS devices, we explore the sources of overhead when using existing programmable systems, and we compare these approaches to an application-specific approach of our own design. In the end we demonstrate that this nature of this problem, both in terms of the required performance and the nature of the working datasize, results in a significant gap that could perhaps be filled by more programmable designs carefully crafted to this domain.

ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific integrated processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms. Keywords Digital Signal Processing (DSP), Architectural Synthesis, Pipelined Architectures, Systolic Architectures, Configurable Architectures, Application Specific Integrated Processors (ASIP) I. Introduction Phenomenal advances in silicon micro-chip technology have b...