. Reconfigurable coprocessors can exploit large degrees of instruction-level parallelism (ILP). In compiling sequential code for reconfigurable coprocessors, we have found it convenient to borrow techniques previously developed for exploiting ILP for very long instruction word (VLIW) processors. With some minor adaptations, these techniques are a natural match for automatic compilation to a reconfigurable coprocessor. This paper will review these techniques in their original context, describe how we have adapted them for reconfigurable computing, and present some preliminary results on compiling application programs written in the C programming language. 1 Introduction In this work we consider compilation for a hybrid reconfigurable computing platform consisting of a microprocessor coupled with field-programmable gate array (FPGA) circuitry used as a reconfigurable accelerator. The FPGA is configured to provide a customized accelerator for compute-intensive tasks. This accel...

In a world of ad-hoc networks, highly interconnected mobile devices and increasingly large supercomputer clusters, students need models of computation that help them think about dynamic and concurrent systems. Many of the tools currently available for introducing students to concurrency are di#cult to use and are not intrinsically motivating. To provide an authentic, hands-on, and enjoyable introduction to concurrency, we have ported occam-#, a language whose expressive powers are especially compelling for describing communicating dynamic reactive processes, to the LEGO Mindstorms.

Stochastic Local Search (SLS) methods have proven to be successful for solving propositional satis ability problems (SAT). In this paper, we show a hardware implementation of the greedy local search proceduce GSAT. With the use of eld programmable gate arrays (FPGAs) , our implementation achieves one ip per clock cycle by exploiting maximal parallelism and at the same time avoiding excessive hardware cost. Experimental evaluation of our prototype design shows a speedup of two orders of magnitude over optimized software implementations and at least one order of magnitude over existing hardware schemes. As far as we are aware, this is the fastest known implementation of GSAT. We also introduce a high level algorithmic notation which is convenient for describing the implementation of such algorithms in hardware, as well as an appropriate performance measure for SLS implementations in hardware.

The role of software-oriented methods, especially programming, is achieving a more and more important role in the design of new systems. This paper demonstrates how an algorithm can be implemented partly in hardware and partly in software on a special FPGA-based reconfigurable computing system platform. We start with an abstract formal specification of the algorithm. Thereafter we show, without being very formal, how the specification is used to map the specification into an implementation. Moreover, the specification helps us in identifying the different software and hardware partitions. Keywords: Codesign, FEAL-8, FPGA TUCS Research Group Programming Methodology Research Group 1 Introduction Reconfigurable computing systems can be defined as systems consisting of a combination of SRAM-based FPGAs, memory, CPUs and DSPs [5]. In many cases, it is the FPGA that makes the system reconfigurable [6, 23]. A reconfigurable computing system can be mounted into a host computer or be connec...

Object-oriented modeling of hardware promises to help deal with design complexity through higher abstraction and better support for reuse. Whereas simulation of such models is rather easy to achieve, synthesis turns out to require the application of quite sophisticated techniques. In this paper, we devise a solution of the foremost problem, optimized synthesis of object-oriented data types. The outlined algorithms have been implemented for an object -oriented dialect of VHDL and may also contribute, possibly in a co-design context, to synthesis from languages such as C++ or Java. We explain our synthesis methods and show their impact with the example of a microprocessor model. 1 Introduction The need to keep productivity up with the growing complexity of hardware units under design has been and continues to be among the most pressing design methodology issues. It has been effectively addressed by design at ever-higher abstraction, from gate via register-transfer to behavioral level, ...

SL is a simple language designed to improve the productivity of hardware design. It is easy to use and it adopts reusable word-level and bit-level descriptions. This results in concise and easily grasped descriptions which give a good overview of the design. Used together with our SLAVE compiler, SL oers a fast way to produce complicated structural VHDL-code. This structural VHDL-code can then be used by Velab VHDL elaborator in order to produce a netlist for Xilinx XC6200 FPGA.