With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. Invited, IEEE Trans. on VLSI, Dec. 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which degr...

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and eficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. Recently, a variety of power estimation techniques have been proposed, most of which are based on: I the use of simplified delay models, and 2 modeling t 1 e long-term behavior of logic signals wit I! probabili-ties. The array of available techniques diger in subtle ways in the assumptions that they make, the accuracy that they provide, and the kinds of circuits that they apply to. In this tutorial, I will survey the many power estimation techniques that have been recently proposed and, in an attempt to make sense of all the variety, I will try to explain the diflerent assumptions on which these techniques are based, and the impact of these as-sumptions on their accuracy and speed.

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review/tutorial of the power estimation techniques that have recently been proposed. IEEE Circuits and Devices Magazine, 1994. 1. Introduction The continuing decrease in feature size and the corresponding increase in chip density and operating frequency have made power consumption a major concern in VLSI design [1, 2]. Modern microprocessors are indeed hot: the PowerPC chip from Motorola consumes 8.5 Watts, the Pentium chip from Intel consumes 16 Watts, and DEC's alpha chip consumes 30 Watts. Excessive power dissipation in integrated circuits not only discourages their use in a portable environment, but also causes overheating, which deg...

In this work, VASP -- Power Simulator is presented which estimates the total power consumed by a design represented at RT Level (Architectural) in VHDL. Power simulation consists of the following tasks: (a) characterization of the module library, (b) simulation of the VHDL structural description. The module library consists of register level modules such as adders, registers, multiplexors. In the VHDL Libary, for each module two architectures exists namely, onebit and n-bit. The one-bit architecture has capacitance measuring code embedded in it. The n-bit architecture is an instantiation of 1-bit architecture using generate statement. Thus the module library characterization is very fast as it is done only for 1-bit architecture. For a given VHDL structural description, it is simulated using a VHDL simulator and a power profile is obtained. Section 1. Introduction Power consumption is becoming one of the key constraints that the designer has to address as early as possible in the des...

This work addresses the problem of estimating power consumption at higher levels of design abstraction namely, behavioral and architectural (RTL) levels. The techniques are employed in a high level synthesis environment known as Profile-Driven Synthesis System (PDSS), to synthesize low power designs. The contributions of this work are: a behavioral profiler, a behavioral power estimator, architectural power estimator architectural power simulation and a low power behavioral synthesis environment -- PDSS. Broadly, for any power estimation technique proposed in this work, there are two distinct steps : (a) Power Characterization of Module Library; and (b) Power estimation for a given design. The first step involves characterizing the RTL parameterized module library (for datapaths) and PLAs (for controllers) for typical power consumption on an input event, as a function of parameters such bit-size, input size, state-size etc. The second step involves using the profile data gathered at ...

We present a profiling based technique for power estimation. This technique is implemented in the pdss (Profile Driven Synthesis System) for the synthesis of low power designs. Initially, each module in the module library is characterized for the average switching capacitance per input vector. The input description is simulated using user-specified set of input vectors to collect the profile data for various operators and carriers. The profile data, in conjunction with the pre-characterized module library is used to estimate the total capacitance switched by each of the valid schedules produced by the pdssmbox mbox scheduler. A valid schedule is one which satisfies other constaints such as area and delay. The schedule with the least switching capacitance estimate is further synthesized to the layout level. Results show an average deviation of 12% compared with the actual switching capacitance values at the layout level. i High Level Profiling Based Low Power Synthesis Technique 1 In...