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Depth Complexity in Object-Parallel Graphics Architectures
- Proceedings of the Seventh Workshop on Graphics Hardware, Eurographics Technical Report Series, ISSN
, 1992
"... We consider a multiprocessor graphics architecture object-parallel if graphics primitives are assigned to processors without regard to screen location, and if each processor completely renders the primitives it is assigned. Such an approach leads to the following problem: the images rendered by all ..."
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Cited by 12 (4 self)
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We consider a multiprocessor graphics architecture object-parallel if graphics primitives are assigned to processors without regard to screen location, and if each processor completely renders the primitives it is assigned. Such an approach leads to the following problem: the images rendered by all processors must be merged, or composited, before they can be displayed. At worst, the number of pixels that must be merged is a frame per processor. Perhaps there is a more parsimonious approach to pixel merging in object-parallel architectures than merging a full frame from each processor. In this paper we analyze the number of pixels that must be merged in object-parallel architectures. Our analysis is from the perspective that the number of pixels to be merged is a function of the depth complexity of the graphics scene to be rendered, and a function of the depth complexity of each processor's subset of the scene to be rendered. We derive a model of depth complexity of graphics scenes ren...
Polygon Rendering For Interactive Visualization On Multicomputers
- Doctoral Dissertation, CS UNC Chapel
, 1996
"... This dissertation identifies a class of parallel polygon rendering algorithms suitable for interactive use on multicomputers, and presents a methodology for designing efficient algorithms within that class. The methodology was used to design a new polygon rendering algorithm that uses the frame-to-f ..."
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Cited by 9 (0 self)
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This dissertation identifies a class of parallel polygon rendering algorithms suitable for interactive use on multicomputers, and presents a methodology for designing efficient algorithms within that class. The methodology was used to design a new polygon rendering algorithm that uses the frame-to-frame coherence of the screen image to evenly partition the rasterization at reasonable cost. An implementation of the algorithm on the Intel Touchstone Delta at Caltech, the largest multicomputer at the time, renders 3.1 million triangles per second. The rate was measured using a 806,640 triangle model and 512 i860 processors, and includes back-facing triangles. A similar algorithm is used in Pixel-Planes 5, a system that has specialized rasterization processors, and which, when introduced, had a benchmark score for the SPEC Graphics Performance Characterization Group "head" benchmark that was nearly four times faster than commercial workstations. The algorithm design methodology also ident...

