Abstract—A low-energy successive approximation analog-todigital converter (ADC) targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation, communications, and power into a tiny volume. Energy is extremely limited, forcing the nodes to operate with very low duty cycles. This paper describes the design and implementation of an ADC to meet the unique requirements of sensor networks. The ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW. This energy consumption is one of the lowest ever reported. Index Terms—Analog-to-digital converter (ADC), charge redistribution, CMOS, energy, low power, sensor networks, Smart Dust, successive approximation.

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. It is important to analyze the fault sensitivities of each of these to eectively gauge and improve the reliability of the system. This paper addresses the issue of fault sensitivity of ADCs. A generic methodology for analyzing the fault sensitivity of ADCs is presented. A novel concept of \node weights" speci c to -particle induced transient faults is introduced to increase the accuracy of such an analysis. 1. Introduction Fault sensitivity analysis allows the testing of the susceptibility of a circuit to dierent kinds of faults. This kind of study is necessary for space, military, avionics and biomedical applications. The purpose of such an analysis is to identify critical blocks in the circuit which are more susceptible to faults so that the...

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an Analog-to-Digital Converter (ADC) to convert the collected data to digital form and a digital unit to process it. Though considerable amount of research has been performed to increase the reliability of digital blocks, the same can not be claimed for mixed signal blocks. The reliability enhancement which we employ starts with fault sensitivity analysis followed by redesign. The data obtained from the sensitivity analysis is used to grade blocks based on their sensitivity to faults. The highly sensitive blocks can then be replaced by more reliable alternatives. The improvement gained by opting for more robust implementations might be limited due to the number of possible implementations. In these cases alternative reliability enhancement techniques such as adding redundancy may provide further improvements. The steps involved in the reliability enhancement of ADCs are illustrated in this paper by first proposing a sensitivity analysis methodology for #-particle induced transients and then suggesting redesign techniques to improve the reliability of the ADC. A novel concept of node weights specific to #-particle transients is introduced which improves the accuracy of the sensitivity analysis. The fault simulations show that, using techniques such as alternative robust implementations, adding redundancy, pattern detection and transistor sizing, considerable improvements in reliability can be attained.

The technology to build highly integrated 3-dimensional computational image sensors by stacking and interconnecting layers of 2-dimensional silicon ICs is being developed. Unlike multi-chip module (MCM-V) packaging, in which interconnect lines are brought to the periphery of a chip stack to achieve vertical integration, this new technology allows virtually unrestricted placement of vertical vias within the interior of the chip. The goal of this development is to enable high speed, high resolution image processing in compact low power wearable systems that would be coupled with a head-mounted display (HMD). Potential applications for these systems include target tracking and image stabilization. In this talk we focus on the architecture of the 3D image sensor, which includes pixel-parallel analog-to-digital conversion and programmable digital processors for pixel and block operations. We show that 3D technology will allow at least an order of magnitude decrease in power dissipation over...