We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (op-amps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal trade-o s among competing performance measures such aspower, open-loop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal trade-o curves relating performance measures such as power dissipation, unity-gain bandwidth, and open-loop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a

A16mm 3 autonomous solar-powered sensor node with bidirectional optical communication for distributed sensor networks has been demonstrated. The device digitizes integrated sensor signals and transmits/receives data over a free-space optical link. The system consists of three die–a 0.25µm CMOS ASIC, a 2.6 mm 2 SOI solar cell array, and a micromachined four-quadrant corner-cube retroreflector (CCR), allowing it to be used in a one-to-many network configuration. The CMOS ASIC includes a photosensor, integrated 3 MHz oscillator, 69 pJ/bit optical receiver, and 31 pJ/sample ADC.

Analog Viterbi decoders are finding widespread use in class-IV partial-response disk-drive applications. These analog realizations are often used because they are smaller and consume less power than their digital counterparts. However, class-IV signaling allows simplifications during Viterbi detection and thus existing analog decoders have limited applications. The purpose of this paper is to develop efficient analog circuits that can be used for general Viterbi detection. To demonstrate the feasibility of the proposed approach, the analog portions of two analog Viterbi decoders were fabricated in a 0.8-m BiCMOS process. With an off-chip digital path memory, operation up to 50 Mb/s is demonstrated. However, simulations indicate that with on-chip digital path memory, speeds on the order of 300 Mb/s can be achieved. The power consumption of the proposed approach is estimated to be 15 mW/state drawn from a single 5-V power supply. Index Terms---Analog, BiCMOS, communications, Viterbi. I...

This paper examines circuit design of buffered routing switches in symmetrical, island-style FPGAs. The effects of switch size, tile length, level-restoring, and slow input slew rates are examined. Two new fanin-based switch designs are used to eliminate nearly all of the increase in delay that arises from fanout with a previous switch design. Alternating between buffers and pass transistors is shown to improve connection delay without fanout by 25%. To take advantage of this, we propose schemes to replace some buffers with pass transistors to simultaneously reduce area and delay. Routing a suite of MCNC benchmark circuits shows that 14% in areadelay, or 7% in delay can be saved using the new switch schemes. Alternatively, approximately 13% in area can be saved with no degradation to delay.

Abstract—A low-energy successive approximation analog-todigital converter (ADC) targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation, communications, and power into a tiny volume. Energy is extremely limited, forcing the nodes to operate with very low duty cycles. This paper describes the design and implementation of an ADC to meet the unique requirements of sensor networks. The ADC reported here consumes 31 pJ/8-bit sample at 1-V supply and 100 kS/s, with a standby power consumption of 70 pW. This energy consumption is one of the lowest ever reported. Index Terms—Analog-to-digital converter (ADC), charge redistribution, CMOS, energy, low power, sensor networks, Smart Dust, successive approximation.

. This work studies the problem of CMOS operational amplifiers design optimisation. The synthesis of CMOS amplifiers can be translated into a multiple-objective optimisation task, in which a large number of specifications has to be taken into account, i.e., GBW, area, power consumption and others. We apply Genetic Algorithms [7] (GAs) to this problem; GAs are a computational optimisation technique which borrows some principles from biological evolution and have been widely applied to Computer Aided Design (CAD) of electronic circuits. A novel multi-objective optimisation methodology is embedded in our genetic algorithm and we focus mainly on the synthesis of micro-power analog cells. 1 Introduction We present a novel methodology applied to the problem of analog CMOS cells optimisation. Particularly, we tackle the issue of synthesising low-power operational amplifiers. The acquisition of micropower analog circuits is a major tendency in the electronics industry nowadays and, an...

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The classification of universal amplifiers presented in this paper places all operational amplifiers and current conveyors known from the literature into a common framework, together with abstract concepts such as the universal active element and the nullor. Our approach is new in that we base it on four-terminal theory, which results in a classification that is more extensive but not more complex than classifications derived using two-port theory. It turns out that our classification contains a new type of operational amplifier, which we call current-feedback operational transconductance amplifier (CFB OTA), and also a new class of voltage-inverting current conveyors. We then demonstrate that our classification is very closely related to integrated-amplifier design by showing how all operational amplifiers and current conveyors can be implemented in CMOS using only a few CMOS circuits. Since the basic ideas behind CMOS and bipolar circuits are very similar, this paper is not process specific and can be seen as an attempt to bridge the gap between amplifier theory and amplifier design that has become ever wider in the past few years.

An on-chip spectrum analyzer using switched-capacitor techniques is described. This system is used for built-in testing analog circuits. The main property of the proposed architecture is its inherent synchronization, which facilitates the testing task saving time, power and silicon area. Simulations and breadboard results are presented in order to verify the main principles. The resolution of the on-chip spectrum analyzer is limited to 8 bits. 1.

This paper presents the analysis and measurements of the impact of digital substrate noise on embedded Analog-to-Digital converters. The impact of substrate noise on analog design is explained, followed by a specific entire impact analysis of the impact on a regenerative comparator and an A/D converter. To confirm the analysis the substrate noise has also been measured on a test chip designed in a 0.35 m heavily--doped-substrate CMOS technology. From the measurements it was deduced that SNR and the effective number of bits are reduced by 20%.