Real-time systems are characterized by the presence of timing constraints in which a task must be completed within a specific amount of time. This paper examines the problem of determining the bound on the worst case execution time (WCET) of a given program on a given processor. There are two important issues in solving this problem: (i) program path analysis, which determines what sequence of instructions will be executed in the worst case, and (ii) microarchitecture modeling, which models the hardware system and determines the WCET of a known sequence of instructions. To obtain a tight estimate on the bound, both these issues must be addressed accurately and efficiently. The latter is becoming difficult to model for modern processors due to the presence of pipelined instruction execution units and cached memory systems. Because of the complexity of the problem, all existing methods that we know of focus only on one of above issues. This limits the accuracy of the estimated bound and the size of the program that can be analyzed. We present a more effective solution that addresses both issues and uses an integer linear programming formulation to solve the problem. This solution is implemented in the program cinderella 1 which currently targets the Intel i960KB processor and we present some experimental results of using this tool. 1

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real-time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time-bound. In our approach, associated with each program construct is what we call a WCTA (Worst Case Timing Abstraction), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning...

... In this paper we present a more effective method for modeling instruction cache activity and computing a tight bound on WCET. The method uses an integer linear programming formulation and does not require explicit enumeration of program paths. The method is implemented in the program cinderella and we present some experimental results of this implementation

We present a method for determining the worst case execution time (WCET) for programs running on systems with modern hardware architectures, e.g. pipelined processors and cache memory. The method is based on the implicit path enumeration technique (IPET), in which all possible execution paths of a program are described by placing constraints on, and relations between, the number of executions of different parts of the program. The execution times for all paths are expressed in terms of those numbers and the maximum execution time is found using optimization (e.g. linear programming). In this paper we present an extension of the IPET which allows different micro-architectural aspects of the execution of programs to be modeled independently. The models are later unified when estimating the WCET. As examples, we show how to model pipelined execution and set-associative caches. Keywords: Hard real-time systems, Worst case execution time, Cache memory, Pipelined execution, Constraint satis...

Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessary when a RISC processor is used as the target processor of a real-time system. However, there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer-based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). This paper proposes two techniques to minimize the WCET overestimation due to such load/store instructions. The first technique uses a global data flow analysis technique to reduce the number of load/store instructions that are misclassified as dynamic load/store instructions. The second technique utilizes data dependence analysis to minimize the adverse impact of dynamic load/store instructions. This paper also compares the WCET bounds of simple benchmark programs that are predicted with and without applying the proposed techniques. The results show that they significantly (up to 20%) improve the accuracy of WCET estimation especially for programs with a large number of references from dynamic load/store instructions. 1.

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Many of the trends that have dominated recent evolution and advancement within the computer architecture community have complicated the analysis of task execution times. Most of the difficulties result from two particular emphases: (1) Instruction-level parallelism, and (2) Optimization of average-case behavior rather than worst-case latencies. Both of these trends have resulted in increased nondeterminism in the time required to execute particular code sequences. And since the analysis required to determine worst-case task execution times on modern processors is so complicated, it is not practical for programmers to perform all of the necessary analyses by hand. Tools must aid them. This paper describes ongoing research on a collection of tools intended to automate the analyses that must be performed in order to build reliable real-time software for modern computing environments. Emphasis is given to the interplay between components of the development environment. 1. Introduction Fo...

This paper presents a generalized admissions control strategy for providing timing guarantees to multimedia applications executing over a set of distributed, heterogeneous system resources. This paper illustrates complications that arise in moving from resource-specific to generalized admissions control and introduces a strategy that can be used to solve some of these problems. Key elements of this Distributed Pipeline Admissions Control Strategy include (i) a resource-independent model for representing multimedia applications requiring access to an heterogeneous set of system resources, (ii) an uniform model for representing a set of heterogeneous system resources, (iii) a real-time heterogeneous resource allocation and routing algorithm, (iv) distributed pipeline scheduling policies that result in efficient and predictable resource usage by clients, and (v) a divide-and-conquer timing analysis technique for ascertaining whether client timing requirements are met. An audio/video examp...

The purpose of this paper is to introduce frameworks based on data-flow equations which provide for estimating the worst-case execution time (WCET) of (real-time) programs. These frameworks allow several different WCET analysis techniques, which range from nave approaches to exact analysis, provided exact knowledge on the program behaviour is available. However, data-flow frameworks can also be used for symbolic analysis based on information derived automatically from the source code of the program. As a byproduct we show that slightly modified elimination methods can be employed for solving WCET data-flow equations, while iteration algorithms cannot be used for this purpose.

Cache memories have been historically avoided in real-time systems because of their unpredictable behavior. In addition to the research focused at obtaining tighter bounds on the worst case execution time of cached programs (typically assuming no preemption), some techniques have been presented to deal with the cache interference due to preemptions (extrinsic or inter-task cache interference). These techniques either account the extrinsic interference in the schedulability analysis, or annuls it by partitioning the cache. This paper describes a new technique, hybrid partitioning, which is a mixture of the former two. It either provides a task with a private partition or accounts for the extrinsic interference that may arise. The hybrid technique outperforms the original two for any workload or hardware configuration. Additionally, this technique is less influenced by those factors. In conclusion, this technique represents a powerful yet general framework for dealing with extrinsic int...