Embedded computer systems are characterized by the presence of a processor running application specific software. A large number of these systems must satisfy real-time constraints. This paper examines the problem of determining the bound on the running time of a given program on a given processor. An important aspect of this problem is determining the extreme case program paths. The state of the art solution here relies on an explicit enumeration of program paths. This runs out of steam rather quickly since the number of feasible program paths is typically exponential in the size of the program. We present a solution for this problem, which considers all paths implicitly by using integer linear programming. This solution is implemented in the program cinderella which currently targets a popular embedded processor -- the Intel i960. The preliminary results of using this tool are presented here.

Real-time systems are characterized by the presence of timing constraints in which a task must be completed within a specific amount of time. This paper examines the problem of determining the bound on the worst case execution time (WCET) of a given program on a given processor. There are two important issues in solving this problem: (i) program path analysis, which determines what sequence of instructions will be executed in the worst case, and (ii) microarchitecture modeling, which models the hardware system and determines the WCET of a known sequence of instructions. To obtain a tight estimate on the bound, both these issues must be addressed accurately and efficiently. The latter is becoming difficult to model for modern processors due to the presence of pipelined instruction execution units and cached memory systems. Because of the complexity of the problem, all existing methods that we know of focus only on one of above issues. This limits the accuracy of the estimated bound and the size of the program that can be analyzed. We present a more effective solution that addresses both issues and uses an integer linear programming formulation to solve the problem. This solution is implemented in the program cinderella 1 which currently targets the Intel i960KB processor and we present some experimental results of using this tool. 1

... In this paper we present a more effective method for modeling instruction cache activity and computing a tight bound on WCET. The method uses an integer linear programming formulation and does not require explicit enumeration of program paths. The method is implemented in the program cinderella and we present some experimental results of this implementation

. The knowledge of program execution times is crucial for the development and the verification of real-time software. Therefore, there is a need for methods and tools to predict the timing behavior of pieces of program code and entire programs. This paper presents a novel method for the analysis of program execution times. The computation of MAximum eXecution Times (MAXTs) is mapped onto a graph-theoretical problem that is a generalization of the computation of a maximum cost circulation in a directed graph. Programs are represented by T-graphs, timing graphs, which are similar to flow graphs. These graphs reflect the structure and the timing behavior of the code. Relative capacity constraints, a generalization of capacity constraints that bound the flow in the edges, express user-supplied information about infeasible paths. To compute MAXTs, T-graphs are searched for those execution paths which correspond to a maximum cost circulation. The search problem is transformed into an integer...

Most structured design methods claim to address the needs of hard real-time systems. However, few contain abstractions which directly relate to common hard real-time activities, such as periodic or sporadic processes. Furthermore, the methods do not constrain the designer to produce systems which can be analysed for their timing properties. In this paper we present a structured design method called HRT-HOOD (Hard Real-Time Hierarchical Object Oriented Design). HRT-HOOD is an extension of HOOD, and includes object types which enable common hard real-time abstractions to be represented. The method is presented in the context of a hard real-time system life cycle, which enables issues of timeliness and dependability to be addressed much earlier on in the development process. We argue that this will enable dependable real-time systems to be engineered in a more cost effective manner than the current practise, which in effect treats these topics as performance issues. To illustrate our appr...

Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. This paper describes three complementary methods to support timing analysis by bounding the number of loop iterations. First, an algorithm is presented that determines the minimum and maximum number of iterations of loops with multiple exits. Second, the loopinvariant variables on which the number of loop iterations depends are identified for which the user can provide minimum and maximum values. Finally, a method is given to tightly predict the execution time of loops whose number of iterations is dependent on counter variables of outer level loops. These methods have been successfully integrated in an existing timing analyzer that predicts the performance for optimized code on a machine that exploits caching and pipelining. The result is tighter timing analysis predictions and less work for the user.

: A concurrent programming system for constructing hard-real-time applications is described. The system is based on a novel semantics of inter-process communication called the real-time producer/consumer (RTP/C) paradigm. Process interactions are modeled as producer/ consumer systems with a timing constraint on the rate at which the consumer must service the producer. The RTP/C paradigm provides a framework both for expressing processor-time-dependent computations and for reasoning about the real-time behavior of programs. A formal model of processor and resource allocation is used to determine necessary and sufficient conditions for realizing the RTP/C semantics of a program. The design of an interactive graphics system illustrates the use of the system. Introduction Real-time computer systems are loosely defined as the class of computer systems that must perform computations and I/O operations in a time-frame defined by processes in the environment external to the computer. Real-time...

This work takes a fresh look at the simulation of cache memories. It introduces the technique of static cache simulation that statically predicts a large portion of cache references. To efficiently utilize this technique, a method to perform efficient on-the-fly analysis of programs in general is developed and proved correct. This method is combined with static cache simulation for a number of applications. The application of fast instruction cache analysis provides a new framework to evaluate instruction cache memories that outperforms even the fastest techniques published. Static cache simulation is shown to address the issue of predicting cache behavior, contrary to the belief that cache memories introduce unpredictability to real-time systems that cannot be efficiently analyzed. Static cache simulation for instruction caches provides a large degree of predictability for real-time systems. In addition, an architectural modification through bit-encoding is introduced that provides fu...

. This paper describes work in progress at the University of York on worst-case timing analysis of software for hard real-time and safety-critical systems. We are pursuing a programming environment that combines the technologies of program proof and timing analysis. In short, the analytical power afforded by a classical program proof tool is ideal for the high-level analysis of timing properties. The main thrust of our work, then, has been to investigate how these technologies can be integrated to their mutual benefit. This paper describes our current ideas and results in this field. 1. Introduction The need for static timing analysis of software for hard real-time systems is well-known. 1-3 Static timing analysis is important for system design and testing and is a prerequisite for static schedulability analysis. This work is also motivated by the needs of safety-critical systems, and through direct collaboration with industry. During case studies of typical hard real-time and critic...

We present TCEL (Time-Constrained Event Language), whose timing semantics is based solely on the constrained relationships between observable events. Using this semantics, the unobservable code can be automatically moved to convert an unschedulable task set into a schedulable one. We illustrate this by an application of program-slicing, which we use to automatically tune control-domain systems driven by ratemonotonic scheduling.