Abstract-We present a novel, highly efficient functional test generation methodology for synchronous sequential circuits. We generate test vectors for the growth (G) and disappearance (D) faults using a cube description of the finite state machine (FSM). Theoretical results establish that these tests guarantee a complete coverage of stuck faults in combinational and sequential circuits, synthesized through algebraic transformations. The truth table of the combinational logic of the circuit is modeled in the form known as personality matrix (PM) and vectors are obtained using highly efficient cube-based test generation method of programmable logic arrays (PLA). Sequential circuits are modeled as arrays of time-frames and new algorithms for state justification and fault propagation through faulty PLA’s are derived. We also give a fault simulation procedure for G and D faults. Experiments show that test generation can be orders of magnitude faster and achieves a coverage of gate-level stuck faults that is higher than a gate-level sequential-circuit test generator. Results on a broad class of small to large synthesis benchmark FSM’s from MCNC support our claim that functional test generation based on G and D faults is a viable and economical alternative to gate level ATPG, especially in a logic synthesis environment. The generated test sequences are implementation-independent and can be obtained even when details of specific implementation are unavailable. For the ISCAS’89 benchmarks, available only in multilevel netlist form, we extract the PM and generate functional tests. Experimental results show that a proper resynthesis improves the stuck fault coverage of these tests. I.

Sequential test generation for large and complex designs, when performed at the gate-level, is known to be a difficult task. Highlevel testing strategies, on the other hand, are less computation intensive, but suffer from accuracy problems. In this paper we propose to exploit high-level information to simplify gate-level test generation. In particular, we propose to compute a set of test sequences starting directly from the VHDL description of the system being synthesized, without any knowledge of the final realization of the design. Such test sequences are then simulated at the gate-level in order to reduce the number of faults for which a test needs to be determined by the gate-level test generation tool, thus allowing substantial time savings. Experimental results, though preliminary, show the effectiveness of the proposed technique. 1 Introduction The advent of powerful hardware description languages (HDLs), such as VHDL, and the development of synthesis techniques accepting, as ...