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Formal Synthesis in Circuit Design  A Classification and Survey
, 1996
"... . This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis m ..."
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Cited by 12 (2 self)
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. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view. 1 Introduction In everyday use, synthesis means putting together of parts or elements so as to make up a complex whole. However in the circuit design domain, synthesis stands for a stepwise refinement of circuit descriptions from higher levels of abstraction (specifications) to lower ones (implementations), including optimizations within one abstraction level. Synthesis can be performed by hand for small circuits. Nowadays mor...
Theorem Proving Guided Development of Formal Assertions in a ResourceConstrained Scheduler for HighLevel Synthesis
 Proceedings of International Conference on Computer Design (ICCD'98
, 1998
"... This paper presents a formal specification and a proof of correctness of the widelyused ForceDirected List Scheduling (FDLS) algorithm for resourceconstrained scheduling of data flow graphs in highlevel synthesis systems. The proof effort is conducted using a higherorder logic theorem prover ..."
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Cited by 7 (2 self)
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This paper presents a formal specification and a proof of correctness of the widelyused ForceDirected List Scheduling (FDLS) algorithm for resourceconstrained scheduling of data flow graphs in highlevel synthesis systems. The proof effort is conducted using a higherorder logic theorem prover. During the proof effort many interesting properties of the FDLS algorithm are discovered. These properties are formally stated and proved in a higherorder logic theorem proving environment. These properties constitute a detailed set of formal assertions and invariants that should hold at various steps in the FDLS algorithm. They are then inserted as programming assertions in the implementation of the FDLS algorithm in a productionstrength highlevel synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the FDLS algorithm produced correct schedules and, (2) in the event of failure, help discover and isolate programming errors in the FDLS impl...
A Constructive Approach towards Correctness of Synthesis  Application within Retiming
 In The European Design & Test Conference
, 1997
"... This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfills the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which ..."
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Cited by 6 (5 self)
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This paper is dedicated to correct synthesis. By correct synthesis we mean, that there is a mathematical proof telling us, that the output circuit description fulfills the input circuit description. There are several ways to achieve correct synthesis. In this paper, we present a novel approach which integrates conventional synthesis algorithms thus guaranteeing the same quality of designs. Our approach is fully automatic, although it is based on rule applications within a theorem prover. We compare our results in the area of retiming to other approaches.
Formally Embedding Existing High Level Synthesis Algorithms
 Correct Hardware Design and Verification Methods, number 987 in Lecture Notes in Computer Science
, 1995
"... This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations. ..."
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Cited by 6 (2 self)
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This paper introduces a general scheme for formally embedding high level synthesis by formulating its basic steps as transformations within higher order logic. A functional representation of a data flow graph is successively refined by means of generic logical transformations.
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a HighLevel Synthesis System
 Proceedings of 11th Conference on Theorem Proving in Higher Or der Logics (TPHOL'98
"... . This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness ..."
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Cited by 3 (3 self)
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. This paper presents a formal specification and a proof of correctness for the register optimization task in highlevel synthesis. A widely implemented register optimization algorithm is modeled in higherorder logic and verified in a theorem prover environment. A rich collection of correctness properties is systematically formulated during the theorem proving exercise. These properties constitute a detailed set of formal assertions that are identified with the invariants at various stages of the algorithm. The formal assertions are then embedded as programming assertions in the implementation of the register optimization algorithm in a productionstrength highlevel synthesis system. When turned on, the programming assertions (1) certify whether a specific run of the highlevel synthesis system produced designs with errorfree register allocation and, (2) in the event of a failure, help discover and isolate programming errors in the implementation. We present a detaile...
RTBA : A Generic BitSliced Bus Architecture for DataPath Synthesis
, 1990
"... Register transfer level (RTL) equations are used to specify the register and ALU datapaths of machine architectures. RTBA (Register Transfer Bus Architecture) is a target architecture for automatic bitsliced VLSI implementation of RTL equations. This article discusses the automatic derivation proce ..."
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Cited by 2 (0 self)
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Register transfer level (RTL) equations are used to specify the register and ALU datapaths of machine architectures. RTBA (Register Transfer Bus Architecture) is a target architecture for automatic bitsliced VLSI implementation of RTL equations. This article discusses the automatic derivation process of a layout from a typical system of RTL equations using a series of behavior preserving transformations. The test results of a chip fabricated using the derived layout are also presented. Extensions to the RTBA transformations, allowing functions in the RTL equations, are presented by deriving the minmax benchmark. This research was supported in part by the National Science Foundation under grants numbered MIP 8707067, MIP 8921842, and DCR 8521497. 1 INTRODUCTION 2 1 Introduction Synthesis can be characterized as the use of transformation steps to translate a specification into an implementation. The behavioral equivalence of source specification and implementation is assured by c...