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2001a) ‘A programmable continuoustime floatinggate fourier processor
 IEEE Transactions on Circuits and Systems II
"... Abstract—We present a programmable continuoustime floatinggate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolitile weight, and then recombines the frequency channels. A digital signal processor would take a ..."
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Cited by 19 (10 self)
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Abstract—We present a programmable continuoustime floatinggate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolitile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a weight and then computing an inverse FFT. We decompose the frequency bands of the incoming signal using the transistoronly version of the autozeroing floatinggate amplifier (AFGA), also termed the capacitively coupled current conveyer (C 4). Each band decomposition is then fed through a floatinggate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using Kirchoff current law to give a bandweighted output of the original signal. We examine many options to reduce secondorder harmonic problems inherent in the singlesided C 4. We present a method for programming arrays of floatinggate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor. Index Terms—Analog floatinggate arrays, floatinggate circuits, programmable analog circuits, programmable analog filters. I.
Correlation learning rule in floatinggate pFET synapses
 in IEEE Int. Symp. Circuits and Systems
, 1999
"... Abstract—We study the weight dynamics of the floatinggate pFET synapse and the effects of the pFET’s gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltag ..."
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Cited by 14 (6 self)
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Abstract—We study the weight dynamics of the floatinggate pFET synapse and the effects of the pFET’s gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form 1 _ = 1 + [], where is a voltage signal on the gate terminal and is a voltage signal on the drain terminal. We obtain this rule by making a linear approximation to the weight dynamics around a given equilibrium point. We develop this approximation by considering the basic functional form of the system dynamics and then examining the effects of the gate and drain voltages on the specifics of this form. Index Terms—Analog learning rules, analog synapses, electron tunneling, floatinggate circuits, hotelectron injection. I.