We discuss the possibility of developing high-quality floating-gate memories and circuits in digital CMOS technologies that have only one layer of polysilicon. Here, the primary concern is whether or not we can get adequate control-gate linearity from MOS capacitors. We employ two experimental proceedures to address this issue and find acceptable floating-gate circuit behavior with MOS capacitors. First, we simultaniously characterize a MOS capacitor and a linear capacitor; the experimental data show that MOS capacitors behave similarly to linear capacitors over a finite, but usable range. Second, we characterize two typical floating-gate MOS circuit primatives, a floating-gate amplifier and a multiple-input translinear element, two basic circuits that rely heavily on the linearity of the capacitors that couple into the floating gates. Our measurements show that floating-gate circuits with MOS-capacitor control gates behave like their counterparts built with linear capacitors over specif...

We describe two systematic procedures for synthesizing mutlipleinput translinear element (MITE) networks that produce an output current that is equal to product of a number of input currents, each of which is raised to an arbitrary rational power. By using the first procedure, we obtain a MITE network, called a two-layer network, that is relatively insensitive to mismatch in the MITE weight values. By using the second procedure, we arrive at a MITE network, called a cascade network, that reduces the fan-in required of each MITE. We illustrate each of these procedures with an example. 1. MITE NETWORKS: THE SYNTHESIS PROBLEM We recently introduced a class of translinear circuits, called multiple -input translinear element (MITE) networks, that accurately embody product-of-power-law relationships in the current signal domain [1--3]. The MITE is a circuit primitive that produces an output current that is exponential in a weighted sum of the MITE's input voltages [2, 4]. For a given produ...

Abstract — A simple methodology for implementation of low-order, current-mode, log-domain filters in CMOS technology is presented. The key transistors in the circuit are operated in weak inversion and in contrast with previous approache s may pass into the triode regime. The concept is particularly suited to implementation in silicon-on-insulator technology, because dielectric isolation of the transistors eliminates leakage currents, and because influence of the body effect on circuit function is limited. Very long time constants, on the order of 1s or more, are obtainable. A simple elaboration of the basic unit circuit allows the time constant to be controlled by a bias current.

This report describes the class of static translinear circuits, which are capable of accurately implementing a wide range of static nonlinear relationships in the current signal domain, such as products, quotients, fixed power-law relationships, vector magnitude, and rational functions. After a brief historical account of the emergence of the class of translinear circuits, we examine the representation of information in translinear circuits and systems. Then, we describe the translinear principle and its application to the analysis and synthesis of translinear-loop circuits, illustrating the processes with several example circuits. We then describe the operation and implementation of a translinear-circuit primitive called the multiple-input translinear element (MITE). From such elements, we build MITE networks, a class of low-voltage translinear circuits that is equivalent to the class of translinear-loop circuits. We describe intuitively the operation of MITE networks. We also describe how to analyze and synthesize such circuits, illustrating these processes with several example circuits.

alberto @ klab.caltech.edu Feature detection and tracking is a fundamental problem in computer vision research. By detecting and tracking fea-tures in an image sequence it is possible to recover informa-tion on both the motion of the viewer and the structure of the environment. We designed and tested a CMOS imager with analog VLSI focal plane computation for feature detection. The chip implements a feature detection algorithm that is suitable for integration in a compact analog VLSI chip. We will review the algorithm, its analog VLSI implementation and resultsfrom the chip. 1