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31
Discrete Logarithms in Finite Fields and Their Cryptographic Significance
, 1984
"... Given a primitive element g of a finite field GF(q), the discrete logarithm of a nonzero element u GF(q) is that integer k, 1 k q  1, for which u = g k . The wellknown problem of computing discrete logarithms in finite fields has acquired additional importance in recent years due to its appl ..."
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Cited by 88 (6 self)
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Given a primitive element g of a finite field GF(q), the discrete logarithm of a nonzero element u GF(q) is that integer k, 1 k q  1, for which u = g k . The wellknown problem of computing discrete logarithms in finite fields has acquired additional importance in recent years due to its applicability in cryptography. Several cryptographic systems would become insecure if an efficient discrete logarithm algorithm were discovered. This paper surveys and analyzes known algorithms in this area, with special attention devoted to algorithms for the fields GF(2 n ). It appears that in order to be safe from attacks using these algorithms, the value of n for which GF(2 n ) is used in a cryptosystem has to be very large and carefully chosen. Due in large part to recent discoveries, discrete logarithms in fields GF(2 n ) are much easier to compute than in fields GF(p) with p prime. Hence the fields GF(2 n ) ought to be avoided in all cryptographic applications. On the other hand, ...
Modular exponentiation on reconfigurable hardware
 ECE Dept., Worcester Polytechnic Institute
, 1999
"... ..."
Complexity and fast algorithms for multiexponentiation
 IEEE Transactions on Computers
, 2000
"... for multiexponentiations ..."
C.: Security on FPGAs; state of the art implementation and attacks
 In: ACM Trans. Embedded Comp. Sys. (TECS
, 2004
"... ..."
The Design Space Layer: Supporting Early Design Space Exploration for CoreBased Designs
"... A novel library layer, called the "design space layer," is proposed, aimed at supporting both, IPbased and traditional "inhouse " design methodologies, during early design space exploration. Strategies for effectively pruning the large design spaces characteristic of systemonc ..."
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Cited by 8 (0 self)
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A novel library layer, called the "design space layer," is proposed, aimed at supporting both, IPbased and traditional "inhouse " design methodologies, during early design space exploration. Strategies for effectively pruning the large design spaces characteristic of systemonchip designs, and for transparently retrieving information on cores adequate for implementing the system components, are supported by the proposed layer. The layer is selfdocumented and highly compartmentalized into hierarchies of classes of design objects, and is thus easily scalable. A design space layer developed for encryption applications is presented and discussed in some detail. 1 Introduction The trend towards developing corebased, systemonchip solutions for complex application specific systems is clearly irreversible. Increasing the level of design integration is quite attractive from a reliability, power consumption, and unitcost perspective. The use of cores, i.e., macrocells developed by thir...
Bipartite Modular Multiplication
, 2005
"... This paper proposes a new fast method for calculating modular multiplication. The calculation is performed using a new representation of residue classes modulo M that enables the splitting of the multiplier into two parts. These two parts are then processed separately, in parallel, potentially doub ..."
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Cited by 5 (0 self)
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This paper proposes a new fast method for calculating modular multiplication. The calculation is performed using a new representation of residue classes modulo M that enables the splitting of the multiplier into two parts. These two parts are then processed separately, in parallel, potentially doubling the calculation speed. The upper part and the lower part of the multiplier are processed using the interleaved modular multiplication algorithm and the Montgomery algorithm respectively. Conversions back and forth between the original integer set and the new residue system can be performed at speeds up to twice that of the Montgomery method without the need for precomputed constants. This new method is suitable for both hardware implementation; and software implementation in a multiprocessor environment. Although this paper is focusing on the application of the new method in the integer field, the technique used to speed up the calculation can also easily be adapted for operation in the binary extended field GF (2 m).
XTR Implementation on Reconfigurable Hardware
 of Lecture Notes in Computer Science
, 2004
"... Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F ∗ p6 with order dividing p 2 − p + 1 by their trace over Fp2. Compared with the usual representation, this one achieves a ratio of three between security size and manipulated d ..."
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Cited by 5 (1 self)
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Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F ∗ p6 with order dividing p 2 − p + 1 by their trace over Fp2. Compared with the usual representation, this one achieves a ratio of three between security size and manipulated data. Consequently very promising performance compared with RSA and ECC are expected. In this paper, we are dealing with hardware implementation of XTR, and more precisely with Field Programmable Gate Array (FPGA). The intrinsic parallelism of such a device is combined with efficient modular multiplication algorithms to obtain effective implementation(s) of XTR with respect to time and area. We also compare our implementations with hardware implementations of RSA and ECC. This shows that XTR achieves a very high level of speed with small area requirements: an XTR exponentiation is carried out in less than 0.21 ms at a frequency beyond 150 MHz.