Register files represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards larger Instruction Level Parallelism (ILP). The energy cost of a register file access depends greatly on the register file circuitry used. This paper compares various register file circuitry techniques for their energy efficiencies, as a function of the architectural parameters such as the number of registers and the number of ports. The Port Priority Selection technique combined with differential reads and low-swing writes was found to be the most energy efficient and provided significant energy savings compared to traditional approaches in the case of large register files. The dependence of register file access energy upon technology scaling is also studied. However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar compute...

At the nanometer scale, the focus of micro-architecture will move from processing to communication. Most general computer architectures to date have been based on a "stored program" paradigm that differentiates between memory and processing and relies on communication over busses and other (relatively) long distance mechanisms. Nanometer-scale electronics -- nanoelectronics - promises to fundamentally change the ground-rules. Processing will be cheap and plentiful, interconnection expensive but pervasive. This will tend to move computer architecture in the direction of locallyconnected, reconfigurable hardware meshes that merge processing and memory. If the overheads associated with reconfigurability can be reduced or even eliminated, architectures based on non-volatile, reconfigurable, finegrained meshes with rich, local interconnect offer a better match to the expected characteristics of future nanoelectronic devices.

...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................

This paper analyzes the impact of nano-scale technology on future circuit design and describes several prototypes of logic and memory applications. Resonant tunneling transistors, single electron transistors, and quantum cellular automata are reviewed as relevant nanoelectronic device categories. In regard to the limited interconnectivity and the sensitivity of the devices to parameter variations we discuss bit level systolic arrays, a propagate instruction array processor, and fault tolerant logic. Furthermore, functional integration, that is the possibility of exploiting quantum effects to obtain a function specific behavior, is illustrated as design technique by compact memory cells and logic families with reduced circuit complexity.

1 Introduction In the past 40 years, the metal-oxide semiconductor field effect transistor (MOSFET) has become the basic building block for almost all computing devices. The steady growth of their popularity is due to the steady shrinking of the feature size which at present has reached 0.1 micron. However, the laws of quantum mechanics and limitations of fabrication techniques may soon prevent the further decrease of feature size. Hence, researchers are investigating several alternatives to the transistor for ultra-dense circuitry. These new devices whose dimensions are on the order of tens of nanometers are called nano-devices and their science is termed nano-technology.

As circuit parametric variations aggravate in advanced technology, yield emerges as an important figure-of-merit in circuit design. Based on a 130nm technology, the yield-energy-delay tradeoffs in low-power circuit optimization are investigated. Using a log-normal statistical model, Monte-Carlo analyses are performed on typical circuit examples, including an inverter chain, NAND gate, and 4-bit adder. While energy reduction can be effectively achieved by tuning supply voltage (V dd ), threshold voltage (V th ), and device width (W), circuit yield degrades during this process. On the other hand, it is observed that performance variability is relatively insensitive to circuit topology and device length (L). Design guidelines for optimizing yield in the presence of parametric variations and energy-delay constraints are proposed.

The placement accuracy and resolution of direct-write patterning tools, in particular the atomic force microscope (AFM), is considered for application to fabricating multi-passband integrated optical filters. Because of its simpler fabrication a grating structure is proposed that consists of identical stripes that are non-periodically spaced. The recently developed pseudorandom encoding method from the field of computer generated holography is modified to effectively assign analog reflectances at each point along the grating by selective withdrawal and offsetting of the stripes from a periodic spacing. An example filter designed by this method has two 1.5 nm bandwidth passbands and-23 dB of rejection for lightly coupled stripes. As with single band filters, the passbands broaden as the coupling increases. A calculation of the coupling coefficient of stripes on a fundamental mode, slab waveguide indicate that stripes on the order of 100 nm in depth and width support low insertion loss, multipassband filtering applications at visible wavelengths. Lines of these dimensions patterned with an AFM on (110) silicon indicate the feasibility of fabricating these filters. These conclusions are specific to current AFM’s that are limited to writing fields of 100 �m. Increased rejection and decreased passband widths will result from incorporating precise field-stitching into future AFM’s.