Results 1  10
of
12
Symbolic model checking for sequential circuit verification
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1994
"... The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuit ..."
Abstract

Cited by 222 (10 self)
 Add to MetaCart
The temporal logic model checking algorithm of Clarke, Emerson, and Sistla [17] is modified to represent state graphs using binary decision diagrams (BDD’s) [7] and partitioned trunsirion relations [lo], 1111. Because this representation captures some of the regularity in the state space of circuits with data path logic, we are able to verify circuits with an extremely large number of states. We demonstrate this new technique on a synchronous pipelined design with approximately 5 x 10^120 states. Our model checking algorithm handles full CTL with fairness constraints. Consequently, we are able to express a number of important liveness and fairness properties, which would otherwise not be expressible in CTL. We give empirical results on the performance of the algorithm applied to both synchronous and asynchronous circuits with data path logic.
Symbolic Model Checking with Partitioned Transition Relations
, 1991
"... We significantly reduce the complexity of BDDbased symbolic verification by using partitioned transition relations to represent state transition graphs. This method can be applied to both synchronous and asynchronous circuits. The times necessary to verify a synchronous pipeline and an asynchronous ..."
Abstract

Cited by 154 (15 self)
 Add to MetaCart
We significantly reduce the complexity of BDDbased symbolic verification by using partitioned transition relations to represent state transition graphs. This method can be applied to both synchronous and asynchronous circuits. The times necessary to verify a synchronous pipeline and an asynchronous stack are both bounded by a low polynomial in the size of the circuit. We were able to handle stacks with over 10 50 reachable states and pipelines with over 10 120 reachable states. 1 Introduction Although methods for verifying sequential circuits by searching their state transition graphs have been investigated for many years, it is only recently that such methods have begun to seem practical. Before, the largest circuits that could be verified had about 10 6 states. Now it is easy to check circuits that have many orders of magnitude more states [3, 5, 6, 7]. The reason for the dramatic increase is the use of special data structures such as binary decision diagrams (BDDs) [2] for...
A Formal Specification Model for Hardware/Software Codesign
 In Proc. of the Intl. Workshop on HardwareSoftware Codesign
, 1993
"... Embedded controllers for reactive realtime applications are implemented as mixed softwarehardware systems. In this paper we present a model for specification, partitioning, and implementation of such systems. The model, called Codesign Finite State Machines (CFSMs), is based on FSMs and is particul ..."
Abstract

Cited by 35 (5 self)
 Add to MetaCart
Embedded controllers for reactive realtime applications are implemented as mixed softwarehardware systems. In this paper we present a model for specification, partitioning, and implementation of such systems. The model, called Codesign Finite State Machines (CFSMs), is based on FSMs and is particularly suited to a specific class of systems with relatively low algorithmic complexity. Preexisting formal specification languages can be used by the designer to specify the intended behavior of the system and mapped into our model. CFSMs use a nonzero unbounded reaction delay model and hence can be indifferently implemented either in hardware or in software. The implementation only restricts the range of variation of some previously undefined delays, thus preserving formal properties of the specification across implementation refinements. The communication primitive, event broadcasting, is lowlevel enough to be implemented efficiently and yet general enough to allow higherlevel mechanism...
A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis
 INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN
, 1992
"... Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis a ..."
Abstract

Cited by 25 (6 self)
 Add to MetaCart
Characterization of the behavior of an asynchronous system depending on the delay of components and wires is a major task facing designers. Some of these delays are outside the designer's control, and in practice may have to be assumed unbounded. The existing literature offers a number of analysis and specification models, but lacks a unified framework to verify directly if the circuit specification admits a correct implementation under these hypotheses. Our aim is to fill exactly this gap, offering both lowlevel (analysisoriented) and highlevel (specificationoriented) models for asynchronous circuits and the environment where they operate, together with strong equivalence results between the properties at the two levels. One interesting side result is the precise characterization of classical static and dynamic hazards in terms of our model. Consequently the designer can check the specification and directly decide if the behavior of any implementation will depend, e.g., on the delays of the signals described by such specification.
We also outline a design methodology based on our models, pointing out how they can be used to select appropriate high
and lowlevel models depending on the desired characteristics of the system.
Technology Mapping for SpeedIndependent Circuits: Decomposition and Resynthesis
, 1997
"... This paper presents theory and practical implementation of a method for multilevel logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (in ..."
Abstract

Cited by 24 (10 self)
 Add to MetaCart
This paper presents theory and practical implementation of a method for multilevel logic synthesis of speedindependent circuits. An initial circuit implementation is assumed to satisfy the monotonous cover conditions but is technology independent. The proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speedindependence. The algorithm applies known efficient algebraic factorization techniques from combinational multilevel logic synthesis, but achieves also boolean simplification and sequential decomposition. The method allows sharing of decomposed logic. 1 Introduction Speedindependent circuits, originating from D.E. Muller's work [11], are hazardfree under the unbounded gate delay model. With recentprogress in developing efficientanalysis and synthesis techniques, supported by CAD tools, this subclass has moved cl...
A RegionBased Theory for State Assignment in SpeedIndependent Circuits
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN
, 1997
"... State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A wellknown example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard ..."
Abstract

Cited by 17 (6 self)
 Add to MetaCart
State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A wellknown example of such a problem is that of complete state coding (CSC), which happens when a pair of different states in a specification has the same binary encoding. A standard way to approach state coding conflicts is to insert new state signals into the original specification in such a way that the original behavior remains intact. This paper
Asynchronous Techniques for SystemonChip Design  Digital circuit designs that are not sensitive to delay promise to allow operation without clocks for future systemsonachip
, 2006
"... SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the ..."
Abstract

Cited by 12 (4 self)
 Add to MetaCart
SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasidelayinsensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALSVone based on synchronizer, the other on stoppable clockVare described and analyzed.
Three Generations of Asynchronous Microprocessors
 IEEE Design and Test of Computers
, 2003
"... Asynchronous VLSI offers low power, modularity, and robustness to physical variations. We describe three generations of asynchronous microprocessors designed at Caltech between 1988 and today, and the evolving circuits and design techniques associated with each of them. I. ..."
Abstract

Cited by 9 (3 self)
 Add to MetaCart
Asynchronous VLSI offers low power, modularity, and robustness to physical variations. We describe three generations of asynchronous microprocessors designed at Caltech between 1988 and today, and the evolving circuits and design techniques associated with each of them. I.
Coupling Technology Mapping, Logic Optimization and State Encoding for SpeedIndependent Circuits
, 1996
"... This paper is aimed at efficiently solving the technology mapping problem for speedindependent circuits. We do not rely on unbounded fanin libraries, nor on user "hints" about how to decompose a circuit into realistic gates. We formulate the implementation problem in the same framework as state enco ..."
Abstract

Cited by 2 (2 self)
 Add to MetaCart
This paper is aimed at efficiently solving the technology mapping problem for speedindependent circuits. We do not rely on unbounded fanin libraries, nor on user "hints" about how to decompose a circuit into realistic gates. We formulate the implementation problem in the same framework as state encoding for asynchronous circuits. Hence we perform logic minimization and technology mapping while doing state encoding . This yields better results than previous techniques that separated the state encoding, technologyindependent implementation and technology mapping steps. We use classical logic synthesis techniques for twolevel logic coupled with correctness conditions developed for unbounded fanin speedindependent implementation. In order to efficiently explore the search space, we use ground objects called regions, that roughly speaking correspond to causal relationships between occurrences of signal transitions. Preliminary experimental results show the effectiveness of the method. 1 I...
A Novel Framework for Solving the State Assignment Problem for EventBased Specifications
"... We propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. We first establish a relation between STGs and finite state machines (FSMs). Then we solve the STG state assignment problem by minimizing the n ..."
Abstract
 Add to MetaCart
We propose a novel framework to solve the state assignment problem arising from the signal transition graph (STG) representation of an asynchronous circuit. We first establish a relation between STGs and finite state machines (FSMs). Then we solve the STG state assignment problem by minimizing the number of states in the corresponding FSM and by using a critical racefree state assignment technique. State signal transitions may be added to the original STG. A lower bound on the number of signals necessary to implement the STG is given. Our technique significantly increases the STG applicability as a specification for asynchronous circuits. 1 Introduction Asynchronous circuits are playing an increasingly important role in digital designs for two main reasons: 1. Interface circuits, which are inevitably asynchronous, are becoming a bottleneck in the design process. The overall system throughput depends heavily on interface circuits, but unlike data paths or synchronous controllers they ...