Results 1  10
of
25
Optimal design of a CMOS opamp via geometric programming
 IEEE Transactions on ComputerAided Design
, 2001
"... We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er ..."
Abstract

Cited by 54 (10 self)
 Add to MetaCart
We describe a new method for determining component values and transistor dimensions for CMOS operational ampli ers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., they are posynomial functions of the design variables. As a result the ampli er design problem can be expressed as a special form of optimization problem called geometric programming, for which very e cient global optimization methods have been developed. As a consequence we can e ciently determine globally optimal ampli er designs, or globally optimal tradeo s among competing performance measures such aspower, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS ampli ers, directly from speci cations. In this paper we apply this method to a speci c, widely used operational ampli er architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeo curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the speci cations for a
A 3.3V SinglePoly CMOS Audio ADC DeltaSigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR
 IEEE J. SolidState Circuits
, 2000
"... This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33leve ..."
Abstract

Cited by 18 (13 self)
 Add to MetaCart
This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33level #ash ADC with digital commonmode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixedsignal ICs with high digital circuit content, singlepoly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of doublepoly capacitors, thickoxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
A 0.9V 67µW Analog FrontEnd using AdaptiveSNR Technique for Digital Hearing Aid
"... Abstract—An analog frontend composed of a preamplifier and a Σ ∆ modulator is proposed and implemented for digital hearing aid chip. Combined gain control (CGC), the technique, which incorporates an automatic gain control (AGC) with an exponential gain control (EGC), is employed to enlarge dynamic ..."
Abstract

Cited by 1 (1 self)
 Add to MetaCart
Abstract—An analog frontend composed of a preamplifier and a Σ ∆ modulator is proposed and implemented for digital hearing aid chip. Combined gain control (CGC), the technique, which incorporates an automatic gain control (AGC) with an exponential gain control (EGC), is employed to enlarge dynamic range and reduce power consumption. The proposed Σ ∆ modulator exploits adaptiveSNR technique, which generates four different SNRs, thereby achieving low power consumption and optimizing performance. The measured power dissipation of the preamplifier is 35µW. In case of Σ∆ modulator, the peak signaltonoise ratio (SNR) is 86dB, the average power consumption is 31.4µW and the variation of SNR is 14dB. The proposed analog frontend dissipates less than 67µW from a single 0.9V supply. The core area of the preamplifier and the Σ ∆ modulator is 0.1mm2 and 0.4mm2, respectively, in a 0.25µm standard CMOS technology. I.
COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY
, 2004
"... Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytic ..."
Abstract
 Add to MetaCart
Integration of analogtodigital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discretetime and continuoustime integration in voltagemode and in currentmode. For high resolution, superiority of switchedcapacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution. Keywords: Analog–digital conversion; sigma–delta modulation; signaltonoise analysis; low voltage CMOS; switched capacitors; switched current. 1.
Systematic Design for Power Minimization of Pipelined AnalogtoDigital Converters
"... In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total power consumption and the total inputreferred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, an optimization algori ..."
Abstract
 Add to MetaCart
In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total power consumption and the total inputreferred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, an optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specific noise requirement is satisfied. To determine the bias current values of operational amplifiers an optimal choice for settling and slewing time parameters is proposed. A practical design example is presented to show the effectiveness of the proposed methodology. 1.
A FrequencyScalable 15bit Incremental ADC for Low Power Sensor Applications
"... Abstract — A 15bit lowpower incremental ADC is designed for sensor applications. The ADC is designed to be frequencyscalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0. ..."
Abstract
 Add to MetaCart
Abstract — A 15bit lowpower incremental ADC is designed for sensor applications. The ADC is designed to be frequencyscalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0.35mm 2. Configured to operate at fullrate as a DeltaSigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83μW from a 1.8V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/s to 1.67kS/s and scaling analog power by up to 500 times. I.
DESIGN AND REALIZATION OF A SINGLE STAGE SIGMADELTA ADC WITH LOW OVERSAMPLING RATIO
"... submitted by ..."
TABLE OF CONTENTS
, 2009
"... I. INTRODUCTION......................................................................................................... 5 Ice hockey in terms and facts....................................................................................... 7 ..."
Abstract
 Add to MetaCart
I. INTRODUCTION......................................................................................................... 5 Ice hockey in terms and facts....................................................................................... 7
A/D Converter With a Modified Noise Transfer Function
"... Abstract—This paper presents a highorder doublesampling singleloop 61 modulation analogtodigital (A/D) converter. The important problem of noise folding in doublesampling circuits is solved here at the architectural level by placing one of the zeros in the modulator’s noise transfer function a ..."
Abstract
 Add to MetaCart
Abstract—This paper presents a highorder doublesampling singleloop 61 modulation analogtodigital (A/D) converter. The important problem of noise folding in doublesampling circuits is solved here at the architectural level by placing one of the zeros in the modulator’s noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourthorder modulator. Through the use of an efficient switchedcapacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourthorder modulator. An experimental 1bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3V supply in a conservative 0.8 m standard CMOS process. Due to the doublesampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signaltonoise ratio and signaltonoiseplusdistortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total. Index Terms—analogtodigital conversion, double sampling, sigmadelta modulation. I.