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38
Optimal Design of a CMOS OpAmp via Geometric Programming
"... We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifi ..."
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Cited by 85 (9 self)
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We describe a new method for determining component values and transistor dimensions for CMOS operational amplifiers (opamps). We observe that a wide variety of design objectives and constraints have a special form, i.e., theyareposynomial functions of the design variables. As a result the amplifier design problem can be expressed as a special form of optimization problem called geometric programming, for which very efficient global optimization methods have been developed. As a consequence we can efficiently determine globally optimal amplifier designs, or globally optimal tradeoffs among competing performance measures such as power, openloop gain, and bandwidth. Our method therefore yields completely automated synthesis of (globally) optimal CMOS amplifiers, directly from specifications. In this paper we apply this method to a specific, widely used operational amplifier architecture, showing in detail how to formulate the design problem as a geometric program. We compute globally optimal tradeoff curves relating performance measures such as power dissipation, unitygain bandwidth, and openloop gain. We show how the method can be used to synthesize robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
A 3.3V SinglePoly CMOS Audio ADC DeltaSigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR
 IEEE J. SolidState Circuits
, 2000
"... This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33leve ..."
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Cited by 19 (13 self)
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This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33level #ash ADC with digital commonmode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixedsignal ICs with high digital circuit content, singlepoly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of doublepoly capacitors, thickoxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
A LowPower Design Methodology for HighResolution Pipelined AnalogtoDigital Converters
 Proceedings of International Symposium on Low Power Electronic Devices (ISLPED), 2003. Pages
"... In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total inputreferred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimi ..."
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Cited by 3 (1 self)
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In this paper a general method to design a pipelined ADC with minimum power consumption is presented. By expressing the total static power consumption and the total inputreferred noise of the converter as functions of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. To determine the bias current values of operational amplifiers, a novel optimal choice for settling and slewing time parameters is proposed applicable to both singlestage and twostage Millercompensated opamp structures. Using the proposed methodology, the optimum values for capacitors, the resolutions and the opamp device sizes of all stages are determined in order to minimize the total power consumption. Design examples are presented and compared with conventional approaches to show the effectiveness of the proposed methodology.
On the optimum design of regulated cascode operational transconductance amplifiers
 In International Symposium on Low Power Electronics and Design
, 1998
"... An optimal design procedure to achieve minimum power consumption for a given technology and gain bandwidth is presented. Regulated cascode gain enhancement is used to ensure sufficient DCgain at minimum gate length transistors. To validate the approach five folded cascode OTA’s have been implemen ..."
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Cited by 2 (0 self)
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An optimal design procedure to achieve minimum power consumption for a given technology and gain bandwidth is presented. Regulated cascode gain enhancement is used to ensure sufficient DCgain at minimum gate length transistors. To validate the approach five folded cascode OTA’s have been implemented, spanning a bias range of 1A 10mA, with measured unitygain bandwidths within 20 % of the designed value. For 17 mW at 3 V, a 0.5 m CMOS OTA achieves 630 MHz with 51 phase margin. The method has been applied in the design of a 3rd order modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dynamic range of 86 dB for a 100 kHz input signal bandwidth. 1
Architectural selection of A/D converters
 In Proceedings of the 40th conference on Design automation
, 2003
"... A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and technology data and has five generic parameter ..."
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A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and technology data and has five generic parameters. The values of these generic parameters can be estimated by analyzing the different converter structures or by means of a fitting procedure using data from published designs. It is shown that the generic parameters have different values for different types of converters. Therefore the tradeoff between speed, resolution, power dissipation and technology parameters depends on the type of converter. It is shown that the calculated figures of merit of the published designs, together with the calculated global tradeoff comprise a surface in the (5 dimensional) design space. This surface makes it possible to accurately predict the power consumption and select the best converter solution for a certain target application. This can then serve as a first step in data converter synthesis or as a power estimator during highlevel system design exploration.
A 0.9V 67µW Analog FrontEnd using AdaptiveSNR Technique for Digital Hearing Aid
"... Abstract—An analog frontend composed of a preamplifier and a Σ ∆ modulator is proposed and implemented for digital hearing aid chip. Combined gain control (CGC), the technique, which incorporates an automatic gain control (AGC) with an exponential gain control (EGC), is employed to enlarge dynamic ..."
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Abstract—An analog frontend composed of a preamplifier and a Σ ∆ modulator is proposed and implemented for digital hearing aid chip. Combined gain control (CGC), the technique, which incorporates an automatic gain control (AGC) with an exponential gain control (EGC), is employed to enlarge dynamic range and reduce power consumption. The proposed Σ ∆ modulator exploits adaptiveSNR technique, which generates four different SNRs, thereby achieving low power consumption and optimizing performance. The measured power dissipation of the preamplifier is 35µW. In case of Σ∆ modulator, the peak signaltonoise ratio (SNR) is 86dB, the average power consumption is 31.4µW and the variation of SNR is 14dB. The proposed analog frontend dissipates less than 67µW from a single 0.9V supply. The core area of the preamplifier and the Σ ∆ modulator is 0.1mm2 and 0.4mm2, respectively, in a 0.25µm standard CMOS technology. I.
Verification of DeltaSigma Converters using Adaptive Regression Modelling
 Proc. ICCAD
, 2000
"... A new verification technique for analogtodigital converters (ADC) is proposed. The ADC is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistorlevel simulation data. Nonidealities in circuit behavior are captured by the adaptive ..."
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A new verification technique for analogtodigital converters (ADC) is proposed. The ADC is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistorlevel simulation data. Nonidealities in circuit behavior are captured by the adaptive regression technique from the collected data. The algorithms have been implemented in a simulation program ARSIM (Adaptive Regression Simulator), which performs data sampling, model building, and simulation. Experimental results using ARSIM are shown on a secondorder modulator, and they demonstrate the effectiveness of our technique as a fast and accurate approach for verifying converters. 1
A FrequencyScalable 15bit Incremental ADC for Low Power Sensor Applications
"... Abstract — A 15bit lowpower incremental ADC is designed for sensor applications. The ADC is designed to be frequencyscalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0. ..."
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Abstract — A 15bit lowpower incremental ADC is designed for sensor applications. The ADC is designed to be frequencyscalable by 1000 times from 1.67S/s to 1.67kS/s. To reduce power, an opamp with class AB characteristics is used. The design was fabricated in 0.18μm CMOS and occupies an area of 0.35mm 2. Configured to operate at fullrate as a DeltaSigma modulator, the ADC achieves 91.8dB peak SNDR while consuming 83μW from a 1.8V supply. Operating as an incremental converter, the ADC powers off periodically to achieve frequency scalability, maintaining 84.7dB to 88.9dB peak SNDR while operating from 1.67S/s to 1.67kS/s and scaling analog power by up to 500 times. I.