Automatic Synthesis of CMOS Digital/Analog Converters by Robert McKinstry Robinson Neff Doctor of Philosophy in Engineering -- Electrical Engineering and Computer Sciences University of California at Berkeley Professor Paul R. Gray, Chair Synthesis of analog functional blocks in integrated circuits offers promise for improved designer productivity. By developing module generators for commonly used analog circuit elements, a synthesis methodology may be matched to a particular application, with approaches and algorithms determined by the particular needs of target circuit type. An analog circuit designer should be able to input design specifications and underlying technology information, and a synthesis methodology should determine circuit parameter values and dimensions, creating the required mask layouts. Slow, tedious design and redesign methods should be replaced by one in which the computer finds minimum cost designs which meet performance requirements. This work implements synthesis methods for a widely used analog block, the digital/analog converter (DAC).

This paper presents a behavioral representation for the class of Nyquist rate A/D converters that captures the nominal behavior, as well as all the statistical variations. To describe noise effects we use a joint probability density function. To describe behavioral effects due to process variations we use a covariance matrix, \Sigma t . Applications of the model include identification of important A/D error sources, efficient computation of the distributions of integral nonlinearity (INL) and differential nonlinearity (DNL), signal-to-noise plus distortion ratio (TSNR), and efficient worst case and Monte Carlo system simulations. Finally, parameter extraction results are presented that agree well with actual measurements. 1 Introduction The verification of data converters poses a significant challenge to the design community, partly due to the need for higher yield at high resolutions, and partly due to the emphasis on predicting converter performance when used in a system since more ...

In analog system design, final verification in the presence of parasitic loading effects is crucial to guarantee functionality of the entire circuit. In this paper, we present a methodology for analog system verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster. 1 Introduction We have proposed a constraint-driven, top-down design methodology for mixed-mode systems[1] that is supported by analog design tools. An integral part of such methodology is the complete verification of the synthesized circuit in the presence of parasitics due to routing, supply variations, and coupling. Because parasitics degrade analog system performance, it is crucial to verify by simulation as completely as possible the circuit functionality in the presence of these second order effects. Existing design methodologies, manual or automatic [2, 3,...