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11
Timed State Space Exploration using POSETS
, 2000
"... This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state ..."
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Cited by 17 (9 self)
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This paper presents a new timing analysis algorithm for efficient state space exploration during the synthesis of timed circuits or the verification of timed systems. The source of the computational complexity in the synthesis or verification of a timed system is in finding the reachable timed state space. We introduce a new algorithm which utilizes geometric regions to represent the timed state space and partially ordered sets (POSETs) to minimize the number of regions necessary. This algorithm operates on specifications sufficiently general to describe practical circuits, as well as other timed systems. The algorithm is applied to several examples showing significant improvement in runtime and memory usage. I. Introduction The fundamental difficulty in circuit synthesis and verification is controlling the state explosion problem. The state spaces representing reasonably sized systems are large even if the timing behavior of the system is not considered. The problem gets even more c...
Timed Circuit Verification Using TEL Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 2001
"... Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord ..."
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Cited by 16 (6 self)
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Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gatelevel circuits. It also presents an algorithm based on partially ordered sets to make the statespace exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gatelevel timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. I.
Relative timing based verification of timed circuits and systems
 In Proc. International Workshop on Logic Synthesis
, 2002
"... Aggressive timed circuits, including synchronous and asynchronous selfresetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing ..."
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Cited by 14 (4 self)
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Aggressive timed circuits, including synchronous and asynchronous selfresetting circuits, are particularly challenging to design and verify due to complicated timing constraints that must hold to ensure correct operation. Identifying a small, sufficient, and easily verifiable set of relative timing constraints simplifies both design and verification. However, the manual identification of these constraints is a complex and errorprone process. This paper presents the first systematic algorithm to generate and optimize relative timing constraints sufficient to guarantee correctness. The algorithm has been implemented in ourRTCG tool and has been applied to several reallife circuits. In all cases, the tool successfully generates a sufficient set of easily verifiable relative timing constraints. Moreover, the generated constraint sets are the same size or smaller than that of the handoptimized constraints. 1.
Partial order reduction for verification of timed systems
, 1999
"... conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government. ..."
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Cited by 10 (0 self)
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conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government.
Correctness and Reduction in Timed Circuit Analysis
, 2002
"... To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these de ..."
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Cited by 10 (1 self)
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To increase performance, circuit designers are experimenting with timed circuits  a class of circuits that rely on a complex set of timing constraints for correct functionality. This is evidenced in published experimental designs from industry. Timing constraints are key to the success of these designs, and algorithms to verify timing constraints are required to make them practical in commercial applications. Due to the complexity of the constraints, however, traditional static timing analysis is not adequate. Timed state space analysis is required; thus, improved timed state space analysis is paramount to producing efficient timed circuits. This diss
Modeling and verifying circuits using generalized relative timing
 In 11th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC
, 2005
"... We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using general ..."
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Cited by 4 (3 self)
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We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verification algorithms for timed automata are then used to either verify a temporal logic property or to check conformance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case studies to demonstrate our approach, including a selftimed circuit used in the integer unit of the Intel R Pentium R 4 processor.
To appear at ASYNC’05 Modeling and Verifying Circuits Using Generalized Relative Timing
"... We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using general ..."
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We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verification algorithms for timed automata are then used to either verify a temporal logic property or to check conformance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case studies to demonstrate our approach, including a selftimed circuit used in the integer unit of the Intel R ¢ R ¢ Pentium 4 processor. 1.
An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow
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Approved for the Major Department
, 2004
"... committee and by majority vote has been found to be satisfactory. ..."
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