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The Notion of Proof in Hardware Verification
, 1989
"... : Recent advances in the field of hardware verification have raised some fresh (and some familiar) issues to do with the scope and limitations of formal proof. In this note, some of these are considered in the context of the Viper verification project. Viper is a microprocessor designed by W. J. Cu ..."
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Cited by 48 (0 self)
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: Recent advances in the field of hardware verification have raised some fresh (and some familiar) issues to do with the scope and limitations of formal proof. In this note, some of these are considered in the context of the Viper verification project. Viper is a microprocessor designed by W. J. Cullyer, C. Pygott and J. Kershaw, of the Royal Signals and Radar Establishment of the U.K. Ministry of Defense, for use in safetycritical applications. Much to their credit, the designers intended from the start that Viper be formally verified; they presented Viper's more abstract specifications in a language suitable for formal reasoning, and they placed the design in the public domain. Viper microprocessors are currently being marketed as verified chips. The formal proof aspects of the verification work have been carried out at the Computer Laboratory of the University of Cambridge. To date, some important properties of a registertransfer level model of Viper, relative to a more abstract ...
A Unified Framework for Design Validation and Manufacturing Test
 IN PROC. INTL. TEST CONF
, 1996
"... New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. In this paper we propose a new direction for solving the test problem using powerful methods already employed for the ..."
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Cited by 13 (3 self)
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New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. In this paper we propose a new direction for solving the test problem using powerful methods already employed for the formal verification of large circuits. More specifically, we will discuss how abstraction techniques can assist conventional ATPG tools when attacking hard to detect faults. The same abstractions can also be used in design verification to increase the level of confidence in a design following simulation, by providing a meaningful measure of the coverage achieved by the verification vectors. In this sense, our approach is geared toward providing a unified framework for design validation and manufacturing test.
Abstraction Techniques for Validation Coverage Analysis and Test Generation
 IEEE TRANSACTIONS ON COMPUTERS
, 1998
"... The enormous state spaces which must be searched when verifying the correctness of, or generating tests for complex circuits, precludes the use of traditional approaches. Difficult and hardtofind abstractions are often required to simplify the circuits and make the problems tractable. This paper p ..."
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Cited by 9 (0 self)
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The enormous state spaces which must be searched when verifying the correctness of, or generating tests for complex circuits, precludes the use of traditional approaches. Difficult and hardtofind abstractions are often required to simplify the circuits and make the problems tractable. This paper presents a simple and automatic method to extract the control flow of a circuit so that the resulting manageable state space can be explored for validation coverage analysis and automatic test generation. This control flow, capturing the essential "behavior" of the circuit, is represented as a finite state machine called the ECFM (Extracted Control Flow Machine). Simulation is currently the primary means of verifying large circuits, but an open problem is the definition of a coverage measure for simulation vectors. We define functional coverage as the amount of control behavior (the ECFM) covered by the test suite, thus providing a pragmatic solution to the problem. We then combine formal ver...
Distributed Binary Decision Diagrams for Verification of Large Circuits
 IEEE Int. Conf. on Comp. Design
, 1996
"... Binary Decision Diagrams are widely used for efficiently representing logic designs and for verifying their equivalence. They usually require large amounts of memory even for relatively small circuits. This paper presents a new mechanism for alleviating this problem by exploiting the memory avail ..."
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Cited by 4 (0 self)
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Binary Decision Diagrams are widely used for efficiently representing logic designs and for verifying their equivalence. They usually require large amounts of memory even for relatively small circuits. This paper presents a new mechanism for alleviating this problem by exploiting the memory available in a cluster of workstations. All the memory required for each node may be allocated in other machines on the network, and any references to the node return the desired item from the appropriate machine in a transparent fashion. Results show that this mechanism is useful in applications which are memory intensive. 1 This research was supported by the Semiconductor Research Corporation under grant 94DP388 and Texas Advanced Technology and Transfer Program under project 3658469 at the University of Texas at Austin 1 Introduction Binary Decision Diagrams (BDDs) are canonical forms for the representation and manipulation of Boolean functions [3]. They can be used to solve a wide v...
Formal Methods: Why Should I Care?  The development of the T800 transputer floatingpoint unit
 In Proc. 13th New Zealand Computer Society Conference
, 1993
"... The term `formal methods' is a general term for precise mathematicallybased techniques used in the development of computer systems, both hardware and software. This paper discusses formal methods in general, and in particular describes their successful role in specifying, constructing and proving c ..."
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Cited by 3 (0 self)
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The term `formal methods' is a general term for precise mathematicallybased techniques used in the development of computer systems, both hardware and software. This paper discusses formal methods in general, and in particular describes their successful role in specifying, constructing and proving correct the floatingpoint unit of the Inmos T800 transputer chip. 1. Introduction The need for reliable computer systems is increasing rapidly, in step with our growing dependence on computers in daily life. This need can only be met by developing more rigorous methods for constructing these systems. The term `formal methods' is a blanket term for such precise, mathematicallybased techniques for the development of computer systems. In this paper, we aim to give an introduction to formal methods in general, and to discuss how they helped in constructing the floatingpoint unit of the Inmos T800 transputer chip. The transputer [Inmos Ltd 1988b] is a microprocessor chip designed specificall...
XMachine Specification and Refinement of Digital Devices
 Department of Computer Science, University of Sheffield
, 1997
"... The purpose of this paper is to investigate the idea of refinement in the context of hardware verification using a general computational model called Xmachines. Developing successive formal models of, for example, microprocessors, is an essential part of the design of such devices. In many case stu ..."
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The purpose of this paper is to investigate the idea of refinement in the context of hardware verification using a general computational model called Xmachines. Developing successive formal models of, for example, microprocessors, is an essential part of the design of such devices. In many case studies the transformation of an abstract high level model into a model which incorporates architectural structure and specific design detail is done on the basis of heuristics and practical implementation issues. This, then, leaves the designer with the task of establishing the correctness of the refined designits equivalence in some sense with the original model. The theory of refinement we present is based on the analysis of such models and has the benefits that the equivalence is achieved by construction. The formalism used, being based on a generalisation of finite state machines, is also closer to the metaphors used by practising designers than many of the other formal specification lang...
Propositional Theorem Proving by Semantic Tree Trimming for Hardware Verification
, 1999
"... The present work describes a new algorithm for testing the satisfiability of statements in propositional logic. It was designed to efficiently handle the most obvious kinds of pathological cases for the DavisPutnam algorithm. Its performance is compared with a very efficient implementation of Davis ..."
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The present work describes a new algorithm for testing the satisfiability of statements in propositional logic. It was designed to efficiently handle the most obvious kinds of pathological cases for the DavisPutnam algorithm. Its performance is compared with a very efficient implementation of DavisPutnam on a large number of problems, and it is shown to be superior. A recentlydeveloped version of DavisPutnam with a related algorithmic enhancement is better still, but it is conjectured that the same enhancement can apply to the present work, with a similar boost in performance.
The Army Fault Tolerant Architecture Conceptual Study
 NASA Contract NAS118565 Task 14 Report, The Charles Stark Draper Laboratory, 555 Technology Square
, 1991
"... Lab.) 140 p G3/&2 ..."
A Unified Validation Framework for VLSI Circuits Using Formal and Abstraction Techniques
"... TEST SEQUENCE CONTROL FAULTS FTGEN ABSTRACT TEST SEQUENCE REDUNDANT FAULT LIST SYSTEM TEST SEQUENCE STRUCTURAL MODEL COMPARE FAULT SIMULATION FUNCTIONAL SPECIFICATION Functional Block User Input Tool Output ATPG BASED SEQUENCE MAPPING Simulation Design Validation Manufacturing ..."
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TEST SEQUENCE CONTROL FAULTS FTGEN ABSTRACT TEST SEQUENCE REDUNDANT FAULT LIST SYSTEM TEST SEQUENCE STRUCTURAL MODEL COMPARE FAULT SIMULATION FUNCTIONAL SPECIFICATION Functional Block User Input Tool Output ATPG BASED SEQUENCE MAPPING Simulation Design Validation Manufacturing Test Figure 6.1: A Unified Framework possible to handle circuits that cannot be handled even when using implicit enumeration techniques. However, even our current approach based on a flattened circuit representation will fail for large real life circuits. Our future research involves developing techniques for the hierarchical extraction of the ECFM at the behavioral level making use of information about the symmetry of the system. This will allow us to deal with larger circuits. Furthermore, we are working on an extension of the transition coverage metric that will allow us to handle sequences of events. Chapter 7 Future Work 7.1 Proposed Research The results presented in the first fiv...
A Case Study for the RealTime Experimental Evaluation of the VIPER Microprocessor
, 1991
"... This paper describes an experiment to evaluate the applicability of the VIPER (Verifiable Integrated Processor for Enhanced Reliability) microprocessor to realtime control. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use ..."
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This paper describes an experiment to evaluate the applicability of the VIPER (Verifiable Integrated Processor for Enhanced Reliability) microprocessor to realtime control. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing digital electronic systems with a high degree of assurance on the system design and implementation correctness. The design of the VIPER microprocessor was guided by several criteria and restricted by engineering and verification methods including: ffl Developing a microprocessor for use in safetycritical applications [4]