We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC instruction set and achieve 30% to 50% reduction in size for SPEC CINT95 programs. Keywords: Compression, Code Density, Code Space Optimization, Embedded Systems Improving Code Density Using Compression Techniques 1 1 Introduction According to a recent prediction by In-Stat Inc., the merchant processor market is set to exceed $60 billion by 1999, and nearly half of that will be for embedded processors. However, by unit count, embedded processors will exceed the number of g...

This paper presents DSP code optimization techniques, which originate from dedicated memory address generation hardware. We define a generic model of DSP address generation units. Based on this model, we present efficient heuristics for computing memory layouts for program variables, which optimize utilization of parallel address generation units. Improvements and generalizations of previous work are described, and the efficacy of the proposed algorithms is demonstrated through experimental evaluation. 1 Introduction & related work Design of embedded VLSI systems in form of heterogeneous single-chip architectures, comprising both hardware and software components, raises new demands on electronic CAD tools. Among the most challenging ones is code generation for embedded DSPs: Limited area for on-chip program ROMs as well as real-time constraints demand for generation of extremely compact code, while high compilation speed is no longer a primary goal. However, current DSP compiler tech...

Compressing the instructions of an embedded program is important for cost-sensitive lowpower control-oriented embedded computing. A number of compression schemes have been proposed to reduce program size. However, the increased instruction density has an accompanying performance cost because the instructions must be decompressed before execution. In this paper, we investigate the performance penalty of a hardware-managed code compression algorithm recently introduced in IBM's PowerPC 405. This scheme is the first to combine many previously proposed code compression techniques, making it an ideal candidate for study. We find that code compression with appropriate hardware optimizations does not have to incur much performance loss. Furthermore, our studies show this holds for architectures with a wide range of memory configurations and issue widths. Surprisingly, we find that a performance increase over native code is achievable in many situations. Keywords: Compression, CodePack, Code...

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. Embedded systems consisting of the application program ROM, RAM, the embedded processor core and any custom hardware on a single wafer are becoming increasingly common in areas such as signal processing. In this paper, we address new code optimization techniques for embedded fixed point DSP processors which have limited on-chip program ROM and include indirect addressing modes using post increment and decrement operations. These addressing modes allow for efficient sequential access but the addressing instructions increase code size. Most of the previous approaches to the problem aim to find a placement or layout of variables in the memory so that it is possible to subsume explicit address pointer manipulation instructions into other instructions as a post-increment or post-decrement operation. Our solution is aimed at transforming the access pattern by using properties of operators such as commutativity so that current algorithms for variable placement are more effective...

Abstract — DSP processors provide dedicated address generation units (AGUs) that are capable of performing address arithmetic in parallel to the main data path. Address assignment, optimization of memory layout of program variables to reduce address arithmetic instructions by taking advantage of the capabilities of AGUs, has been studied extensively for single functional unit (FU) processors. In this paper, we exploit address assignment and scheduling for multiple-FU processors. We propose an efficient address assignment and scheduling algorithm for multiple-FU processors. Experimental results show that our algorithm can greatly reduce schedule length and address operations on multiple-FU processors compared with the previous work. Index Terms — address assignment, scheduling, multiple functional units, AGU, DSP.

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