Current tools for VLSI placement are based either on quadratic placement, or on min-cut heuristics, or on simulated annealing. For the most complex chips with millions of movable objects, algorithms based on quadratic placement seem to yield the best results within reasonable time. In this paper we prove several new theoretical results on quadratic placement. We point out connections to random walks and electrical networks. Moreover, we argue that quadratic placement has, in contrast to the other approaches, some well-defined stability properties. Finally, we consider the question how to choose the weights of the clique edges representing a multiterminal net optimally.

This thesis examines methods for generation of heterogeneous reconfigurable hardware based on formal optimisation methods. As reconfigurable hardware has evolved, an increasing number of different embedded component types have been made available on reconfigurable devices. Existing techniques for generating hardware and analysing the advantages of different embedded com-ponents are heuristic based, and hence not provably optimal, indeed, even the meaning of “optimal” in such a setting is disputed. Using formal optimisa-tion in the form of integer linear programming, it is possible to determine the advantages of such components analytically for the first time. Moreover, it is possible to use such techniques to determine technology mapping and floor-planning of target designs and floorplanning of architectures concurrently and optimally. In addition, this thesis covers aspects concerning the scalability of integer linear programming. Heuristic methods to solve larger, more complex prob-lems are detailed. The heuristics have been developed so as to be scalable for large, complex designs. The methods introduced in this thesis allow reconfigurable architectures to be tailored to the specific needs of a given set of circuits. In this thesis, existing reconfigurable devices are modelled in order to prove the advantages of embedded components, and to indicate what type of improvement is achievable over existing commercially manufactured devices.

Abstract—Computer-aided design (CAD) tools are now making it possible to automate many aspects of the design process. This has mainly been made possible by the use of effective and efficient algorithms and corresponding software structures. The very large scale integration (VLSI) design process is extremely complex, and even after breaking the entire process into several conceptually easier steps, it has been shown that each step is still computationally hard. To researchers, the goal of understanding the fundamental structure of the problem is often as important as producing a solution of immediate applicability. Despite this emphasis, it turns out that results that might first appear to be only of theoretical value are sometimes of profound relevance to practical problems. VLSI CAD is a dynamic area where problem definitions are continually changing due to complexity, technology and design methodology. In this paper, we focus on several of the fundamental CAD abstractions, models, concepts and algorithms that have had a significant impact on this field. This material should be of great value to researchers interested in entering these areas of research, since it will allow them to quickly focus on much of the key material in our field. We emphasize algorithms in the area of test, physical design, logic synthesis, and formal verification. These algorithms are responsible for the effectiveness and efficiency of a variety of CAD tools. Furthermore, a number of these algorithms have found applications in many other domains. Index Terms—Algorithms, computer-aided design, computational complexity, formal verification, logic synthesis, physical design, test. I.

Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems. Recently, a new Monte Carlo and optimization method, named dynamic weighting Monte Carlo [WL97], has been introduced and successfully applied to the traveling salesman problem, neural network training [WL97], and spin-glasses simulation [LW98]. In this paper, we have successfully applied dynamic weighting Monte Carlo algorithm to the constrained floorplan design with consideration of both area and wirelength minimization. Our application scenario is the constrained floorplan design for mixed signal MCMs, where we need to place all the analog modules together in groups so that they can share common power and ground planes, which are separate from those used by the digital modules. Our experiments indicate that the dynamic weighting Monte Carlo algorithm is very effective for constrained floorplan optimization. It outperforms the simulated annealing for a real mixed signal MCM design by £¥¤§¦©¨� � in wirelength, while gets slight area improvement. This is the first work adopting the dynamic weighting Monte Carlo optimization method for solving VLSI CAD problems. We believe that this method has applications to many other VLSI CAD optimization problems. 1

To my mother and father, for their love, support, and guidance iii ACKNOWLEDGMENTS First and foremost, I would like to thank my adviser, Professor Nick Carter, for his guidance and support during this endeavor. Without his encouragement and ability to help me step back and look at the big picture, this thesis would not have been possible. Next, I would like to thank Derek Gottlieb and Josh Walstrom for the numerous stimulating technical discussions and for the simulation infrastructure used to gather the results for this thesis. To both Lee Baugh and Brian Greskamp, thank you for the innumerable discussions on the intermediate program representation that were invaluable to this thesis. Thanks also to Chi-Wei Wang and Chris Grier for your contributions to the benchmark suite. Many thanks to my brother, Steve, who spent far too many hours reviewing the text of this thesis. I also wish to thank my parents. Your years of support and encouragement have not gone unnoticed. Lastly, to my love, Tara, thank you for your unconditional love and daily support.

Abstract — Y-interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0 ◦ , 60 ◦ , and 120 ◦. Though X-interconnects are fast replacing the traditional Manhattan (M) interconnects, the very recently proposed Y-interconnects have been observed to possess certain key advantages. Y-interconnects tend to consume less routing resources than M-interconnects. Unlike the X-interconnect architectures, Y-interconnect architectures support regular routing grid. This is indeed very important for simplifying manufacturing processes and applying the routing and design rule checking algorithms. Several efficient Y-routing algorithms have been proposed in literature. However, to the best of our knowledge, not much have been reported so far in designing algorithms for Y-interconnectbased VLSI module placement and its effects on the congestion or wire-lengths. In this paper, in an attempt to fill the gap in the existing literature, we propose a novel simulated-annealing-based placement technique for mixed-sized cells which tries to reduce the congestion for Y-interconnects. The proposed method attempts to reduce the congestion, and observes the corresponding changes in the estimated lengths of the Y-interconnects. It has been implemented in Linux environment and experiments performed with randomly generated instances, and some well-known benchmarks. The wirelength estimates for the Y-interconnects, and Manhattan interconnects for the same placement instances are compared. Results obtained are quite encouraging. The experimental results for a specific number of iterations and cooling schedule show improvements in congestion in most of the cases. I.

The design of modern integrated circuits is overwhelmingly complicated due to the enormous number of cells in a typical modern circuit. To deal with this di#culty, the design procedure is broken down into a set of disjoint tasks. Circuit layout is the task that refers to the physical realization of a circuit from its functional description. In circuit layout, a connection-list called netlist of cells and nets is given. Placement and routing are subtasks associated with circuit layout and involve determining the geometric locations of the cells within the placement area and connecting cells sharing common nets. In performing the placement and the routing of the cells, minimum placement area, minimum delay and other performance constraints need to be observed.

Abstract—Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern very large scale integration (VLSI) floorplanning typically needs to pack blocks within a fixed die (outline), and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. In this paper, the authors study two types of modern floorplanning problems: 1) fixed-outline floorplanning and 2) bus-driven floorplanning (BDF). This floorplanner uses B ∗-tree floorplan representation based on fast three-stage simulated annealing (SA) scheme called Fast-SA. For fixed-outline floorplanning, the authors present an adaptive Fast-SA that can dynamically change the weights in the cost function to optimize the wirelength under the outline constraint. Experimental results show that this floorplanner can achieve 100 % success rates efficiently for fixed-outline floorplanning with various aspect ratios. For the BDF, the authors explore the feasibility conditions of the B ∗-tree with the bus constraints, and develop a BDF algorithm based on the conditions and Fast-SA. Experimental results show that this floorplanner obtains much smaller dead space for the floorplanning with hard/soft macro blocks, compared with the most recent work. In particular, this floorplanner is more efficient than the previous works. Index Terms—Floorplanning, physical design. I.

Stochastic combinatorial optimization techniques, such as simulated annealing and genetic algorithms, have become increasingly important in design automation as the size of design problems have grown and the design objectives have become increasingly complex. However, stochastic algorithms are often slow since a large number of random design perturbations are required to achieve an acceptable result -- they have no built-in "intelligence". In this paper, we show that incremental, statistical learning techniques can improve the quality of results and reduce the number of expensive cost-function evaluations for stochastic optimization for a particular solution quality. In particular, simulated annealing was selected as representative stochastic optimization approach and the cell-based layout placement problem was used to evaluate the utility of such a learning-based approach. In this work, we used regression to learn the properties of the solution space and have tested the trained algori...

Abstract—Recent advances in microfluidics technology have led to the emergence of miniaturized biochip devices, also referred to as lab-on-a-chip, for biochemical analysis. A promising category of microfluidic biochips relies on the principle of electrowetting-ondielectric, whereby discrete droplets of nanoliter volumes can be manipulated using an array of electrodes. As chemists adapt more bioassays for concurrent execution on such “digital ” droplet-based microfluidic platforms, system integration, design complexity, and the need for defect tolerance are expected to increase rapidly. Automated design tools for defect-tolerant and multifunctional biochips are important for the emerging marketplace, especially for lowcost, portable, and disposable devices for clinical diagnostics. We present a unified synthesis method that combines defect-tolerant architectural synthesis with defect-aware physical design. The proposed approach allows architectural-level design choices and defect-tolerant physical design decisions to be made simultaneously. We use a large-scale protein assay and the polymerase chain reaction procedure as case studies to evaluate the proposed synthesis method. We also carry out simulations based on defect injection to evaluate the robustness of the synthesized biochip designs. Index Terms—Lab-on-a-chip, microfluidics.