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Algorithms for the Satisfiability (SAT) Problem: A Survey
 DIMACS Series in Discrete Mathematics and Theoretical Computer Science
, 1996
"... . The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computeraided design, computeraided manufacturing, machine vision, database, robotics, integrated circuit design, compute ..."
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Cited by 127 (3 self)
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. The satisfiability (SAT) problem is a core problem in mathematical logic and computing theory. In practice, SAT is fundamental in solving many problems in automated reasoning, computeraided design, computeraided manufacturing, machine vision, database, robotics, integrated circuit design, computer architecture design, and computer network design. Traditional methods treat SAT as a discrete, constrained decision problem. In recent years, many optimization methods, parallel algorithms, and practical techniques have been developed for solving SAT. In this survey, we present a general framework (an algorithm space) that integrates existing SAT algorithms into a unified perspective. We describe sequential and parallel SAT algorithms including variable splitting, resolution, local search, global optimization, mathematical programming, and practical SAT algorithms. We give performance evaluation of some existing SAT algorithms. Finally, we provide a set of practical applications of the sat...
VLSI cell placement techniques
 ACM Computing Surveys
, 1991
"... VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasi ..."
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Cited by 75 (0 self)
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VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro
Spectral Partitioning: The More Eigenvectors, the Better
 PROC. ACM/IEEE DESIGN AUTOMATION CONF
, 1995
"... The graph partitioning problem is to divide the vertices of a graph into disjoint clusters to minimize the total cost of the edges cut by the clusters. A spectral partitioning heuristic uses the graph's eigenvectors to construct a geometric representation of the graph (e.g., linear orderings) which ..."
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Cited by 69 (3 self)
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The graph partitioning problem is to divide the vertices of a graph into disjoint clusters to minimize the total cost of the edges cut by the clusters. A spectral partitioning heuristic uses the graph's eigenvectors to construct a geometric representation of the graph (e.g., linear orderings) which are subsequently partitioned. Our main result shows that when all the eigenvectors are used, graph partitioning reduces to a new vector partitioning problem. This result implies that as many eigenvectors as are practically possible should be used to construct a solution. This philosophy isincontrast to that of the widelyused spectral bipartitioning (SB) heuristic (which uses a single eigenvector to construct a 2way partitioning) and several previous multiway partitioning heuristics [7][10][16][26][37] (which usek eigenvectors to construct a kway partitioning). Our result motivates a simple ordering heuristic that is a multipleeigenvector extension of SB. This heuristic not only signi cantly outperforms SB, but can also yield excellent multiway VLSI circuit partitionings as compared to [1] [10]. Our experiments suggest that the vector partitioning perspective opens the door to new and effective heuristics.
An Industrial View of Electronic Design Automation
 IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
, 2000
"... The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and viceversa. This paper reviews the technologies, algorithms, and methodologies ..."
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Cited by 6 (1 self)
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The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and viceversa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation /verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.
New Iterative Linear Solvers For Parallel Circuit Simulation
 AGENCY USE ONLY (Leave blank) 2. REPORT DATE 3. REPORTTYPE AND DATES COVERED 4. TITLE AND SUBTITLE 5. FUNDING NUMBERS 6. AUTHOR(S) 8. PERFORMING ORGANIZATION REPORT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 9. SPONSORING/MONITORING AGENCY
, 1996
"... This thesis discusses iterative linear solvers for parallel transient analysis of large scale logic circuits. The increasing importance of large scale circuit simulation is the driving force of the researches on efficient parallel circuit simulation. The most time consuming part of circuit transient ..."
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Cited by 4 (0 self)
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This thesis discusses iterative linear solvers for parallel transient analysis of large scale logic circuits. The increasing importance of large scale circuit simulation is the driving force of the researches on efficient parallel circuit simulation. The most time consuming part of circuit transient analysis is the model evaluation, and the next is the linear solver, which takes about 1/5 of simulation time. Although the model evaluation is easy to parallelize in high efficiency, the linear solver is the main obstacle against efficient parallel circuit simulation. The reason of low parallel efficiency in linear solvers is the low parallelism of the direct method based on the LU decomposition. There are some researches on parallel circuit simulation with iterative linear solvers, but problems such as applicability and performance are remaining. This thesis introduces two classes of iterative linear solvers for parallel circuit transient analysis. The first one is the preconditioned rel...
PARALLEL ALGORITHMS FOR PLACEMENT AND ROUTING IN VLSI DESIGN
, 1991
"... The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or paral ..."
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Cited by 2 (0 self)
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The computational requirements for high quality synthesis, analysis, and verification of VLSI designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the tirn,e required for solution. In this thesis, we propose two new parallel algorithms for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithrr{, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, we present results which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs, and we present measurements on the parallel speedups available.
ArchitectureAware FPGA Placement using Metric Embedding
 DAC 2006
, 2006
"... Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architectureaware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our appro ..."
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Cited by 2 (0 self)
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Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architectureaware approach to initial FPGA placement that models the relationship between performance and the routing grid, using concepts from graph embedding and metric geometry. Our approach, CAPRI, can be viewed as an embedding of a graph representing the netlist into a metric space that is representative of the FPGA. First, we develop an analytic metric of distance that models delays along the FPGA routing grid. We then embed a netlist into the defined metric space using matrix projections and online bipartite matching. Experimental comparisons with the popular FPGA tool, VPR, show that with CAPRI’s initial solution, the resulting placements show median improvements of 10% in critical path delays for the larger MCNC benchmarks. Total placement runtime is also improved by 2x on average.
Efficient Final Placement Based on NetsAsPoints
 In Proceedings of The 26th DAC
, 1989
"... Deterministic optimization programs are coming to be considered as viable alternatives for the placement of very large seaofgate, gate array and standard cell designs. A netsaspoints placement program has been described which provides competitive results in comparison with nondeterministic pla ..."
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Cited by 1 (0 self)
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Deterministic optimization programs are coming to be considered as viable alternatives for the placement of very large seaofgate, gate array and standard cell designs. A netsaspoints placement program has been described which provides competitive results in comparison with nondeterministic placement, and at a fraction of the run time. A new pseudo Steiner tree model for the gate placement about the netpoints, along with a virtual channel snaptogrid procedure, provides results superior to the original netsaspoints placement program without requiring iterative improvement.
VEAP: Global Optimization based Efficient Algorithm for VLSI Placement
"... Abstract In this paper we present a very simple, efficient while effective placement algorithm for Rowbased VLSIs. This algorithm is based on strict mathematical analysis, and provably can find the global optima. From our experiments, this algorithm is one of the fastest algorithms, especially fo ..."
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Abstract In this paper we present a very simple, efficient while effective placement algorithm for Rowbased VLSIs. This algorithm is based on strict mathematical analysis, and provably can find the global optima. From our experiments, this algorithm is one of the fastest algorithms, especially for very large scale circuits. Another point desired to point out is that our algorithm can be run in both wirelength and timingdriven modes. I.