Results 1  10
of
76
Geometric Shortest Paths and Network Optimization
 Handbook of Computational Geometry
, 1998
"... Introduction A natural and wellstudied problem in algorithmic graph theory and network optimization is that of computing a "shortest path" between two nodes, s and t, in a graph whose edges have "weights" associated with them, and we consider the "length" of a path to be the sum of the weights of t ..."
Abstract

Cited by 147 (12 self)
 Add to MetaCart
Introduction A natural and wellstudied problem in algorithmic graph theory and network optimization is that of computing a "shortest path" between two nodes, s and t, in a graph whose edges have "weights" associated with them, and we consider the "length" of a path to be the sum of the weights of the edges that comprise it. Efficient algorithms are well known for this problem, as briefly summarized below. The shortest path problem takes on a new dimension when considered in a geometric domain. In contrast to graphs, where the encoding of edges is explicit, a geometric instance of a shortest path problem is usually specified by giving geometric objects that implicitly encode the graph and its edge weights. Our goal in devising efficient geometric algorithms is generally to avoid explicit construction of the entire underlying graph, since the full induced graph may be very large (even exponential in the input size, or infinite). Computing an optimal
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
Abstract

Cited by 103 (32 self)
 Add to MetaCart
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
The Steiner problems with edge lengths 1 and 2
 INFORMATION PROCESSING LETTERS
, 1989
"... The Steiner problem on networks asks for a shortest subgraph spanning a given subset of distinguished vertices. We give a 4/3approximation algorithm for the special case in which the underlying network is complete and all edge lengths are either 1 or 2. We also relate the Steiner problem to a compl ..."
Abstract

Cited by 77 (1 self)
 Add to MetaCart
The Steiner problem on networks asks for a shortest subgraph spanning a given subset of distinguished vertices. We give a 4/3approximation algorithm for the special case in which the underlying network is complete and all edge lengths are either 1 or 2. We also relate the Steiner problem to a complexity class recently defined by Papadimitriou and Yannakakis by showing that this special case is MAX SNPhard, which may be evidence that the Steiner problem on networks has no polynomialtime approximation scheme.
VLSI cell placement techniques
 ACM Computing Surveys
, 1991
"... VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasi ..."
Abstract

Cited by 75 (0 self)
 Add to MetaCart
VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro
Approximating Geometrical Graphs Via Spanners and Banyans
, 1998
"... The main result of this paper is an improvement of Arora's method to find (1+ ffl) approximations for geometric NPhard problems including the Euclidean Traveling Salesman Problem and the Euclidean Steiner Minimum Tree problems. For fixed dimension d and ffl, our algorithms run in O(N log N) time. ..."
Abstract

Cited by 61 (0 self)
 Add to MetaCart
The main result of this paper is an improvement of Arora's method to find (1+ ffl) approximations for geometric NPhard problems including the Euclidean Traveling Salesman Problem and the Euclidean Steiner Minimum Tree problems. For fixed dimension d and ffl, our algorithms run in O(N log N) time. An interesting byproduct of our work is the definition and construction of banyans, a generalization of graph spanners. A (1 + ffl)banyan for a set of points A is a set of points A 0 and line segments S with endpoints in A [ A 0 such that a 1 + ffl optimal Steiner Minimum Tree for any subset of A is contained in S. We give a construction for banyans such that the total length of the line segments in S is within a constant factor of the length of the minimum spanning tree of A, and jA 0 j = O(jAj), when ffl and d are fixed. In this abbreviated paper, we only provide proofs of these results in two dimensions. The full paper on WDS's web page (http://www.neci.nj.nec.com/homepages/wds, c...
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing
 IN PROC. DESIGN AUTOMATION CONF
, 1996
"... We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay tradeoff curve. We achieve this goal by limiting the solution space to the s ..."
Abstract

Cited by 48 (1 self)
 Add to MetaCart
We present new algorithms for construction of performance driven Rectilinear Steiner Trees under the Elmore delay model. Our algorithms represent a departure from previous approaches in that we derive an explicit area/delay tradeoff curve. We achieve this goal by limiting the solution space to the set of topologies induced by a permutation on the sinks of the net. This constraint allows efficient identification of optimal solutions while still providing a rich solution space. Our approach also incorporates simultaneous wire sizing. Experimentally we have observed that routing topologies produced by previously proposed approaches consume up to 70% more area on average than topologies achieving equal or better delay produced by our algorithm. Our approach has also yielded improved minimum delay and has been adapted to improve a given routing topology for area minimization with good results.
Closing the Gap: NearOptimal Steiner Trees in Polynomial Time
 IEEE Trans. ComputerAided Design
, 1994
"... The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In ..."
Abstract

Cited by 42 (13 self)
 Add to MetaCart
The minimum rectilinear Steiner tree (MRST) problem arises in global routing and wiring estimation, as well as in many other areas. The MRST problem is known to be NPhard, and the best performing MRST heuristic to date is the Iterated 1Steiner (I1S) method recently proposed by Kahng and Robins. In this paper we develop a straightforward, efficient implementation of I1S, achieving a speedup factor of three orders of magnitude over previous implementations. We also give a parallel implementation that achieves nearlinear speedup on multiple processors. Several performanceimproving enhancements enable us to obtain Steiner trees with average cost within 0.25% of optimal, and our methods produce optimal solutions in up to 90% of the cases for typical nets. We generalize I1S and its variants to three dimensions, as well as to the case where all the pins lie on k parallel planes, which arises in, e.g., multilayer routing. Motivated by the goal of reducing the running times of our algorith...
New Approximation Algorithms for the Steiner Tree Problems
 Journal of Combinatorial Optimization
, 1995
"... The Steiner tree problem asks for the shortest tree connecting a given set of terminal points in a metric space. We design new approximation algorithms for the Steiner tree problems using a novel technique of choosing Steiner points in dependence on the possible deviation from the optimal solutions. ..."
Abstract

Cited by 42 (5 self)
 Add to MetaCart
The Steiner tree problem asks for the shortest tree connecting a given set of terminal points in a metric space. We design new approximation algorithms for the Steiner tree problems using a novel technique of choosing Steiner points in dependence on the possible deviation from the optimal solutions. We achieve the best up to now approximation ratios of 1.644 in arbitrary metric and 1.267 in rectilinear plane, respectively. Dept. of Computer Science, University of Bonn, 53117 Bonn, and International Computer Science Institute, Berkeley, California. Supported in part by the Leibniz Center for Research in Computer Science, by DFG Grant KA 673/41, by the ESPRIT BR Grants 7097 and by ECUS030. Email: marek@cs.unibonn.de. y Institute of Mathematics, 277028 Kishinev, Moldova. Research partially supported by Volkswagen Stiftung. Parts of this work were done in Max Planck Institute fur Informatik, Saarbrucken. Email: 17azz@mathem.moldova.su. 1 Introduction We consider a metric space wi...
On Wirelength Estimations for RowBased Placement
, 1998
"... Wirelength estimation in VLSI layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during topdown floorplanning and placement of cellbased designs. Our methods ..."
Abstract

Cited by 31 (10 self)
 Add to MetaCart
Wirelength estimation in VLSI layout is fundamental to any predetailed routing estimate of timing or routability. In this paper, we develop efficient wirelength estimation techniques appropriate for wirelength estimation during topdown floorplanning and placement of cellbased designs. Our methods give accurate, lineartime approaches, typically with sublinear time complexity for dynamic updating of estimates (e.g., for annealing placement). Our techniques offer advantages not only for early online wirelength estimation during topdown placement, but also for a posteriori estimation of routed wirelength given a final placement. In developing these new estimators, we have made several contributions, including (i) insight into the contrast between regionbased and bounding boxbased RStMT estimation techniques; (ii) empirical assessment of the correlations between pin placements of a multipin net that is contained in a block; and (iii) new wirelength estimates that are functions of a...
An Approach To A Problem In Network Design Using Genetic Algorithms
, 1995
"... In the work of communications network design there are several recurring themes: maximizing flows, finding circuits, and finding shortest paths or minimal cost spanning trees, among others. Some of these problems appear to be harder than others. For some, effective algorithms exist for solving them, ..."
Abstract

Cited by 31 (0 self)
 Add to MetaCart
In the work of communications network design there are several recurring themes: maximizing flows, finding circuits, and finding shortest paths or minimal cost spanning trees, among others. Some of these problems appear to be harder than others. For some, effective algorithms exist for solving them, for others, tight bounds are known, and for still others, researchers have few clues towards a good approach. One of these latter, nastier problems arises in the design of communications networks: the Optimal Communication Spanning Tree Problem (OCSTP). First posed by Hu in 1974, this problem has been shown to be in the family of NPcomplete problems. So far, a good, generalpurpose approximation algorithm for it has proven elusive. This thesis describes the design of a genetic algorithm for finding reliably good solutions to the OCSTP. The genetic algorithm approach was thought to be an appropriate choice since they are computationally simple, provide a powerful parallel search capability...