Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is ...

During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy. 1 Hierarchical Circuit Design An increasing percentage of IC's have analog circuit designs in them. These and other requirements stress the need for automatic synthesis tools for analog circuits. Hierarchy plays a significant role in the design of digital and analog circuits. A large design can be broken up into smaller sub-blocks at the different levels of a hierarchy. An example hierarchy for an A/D converter ...

With the development of increasingly complex microelectrofluidic devices and systems, system-level performance analysis is becoming an important aspect of design. System-level performance analysis is challenging because coupled-energy dynamics link system-level performance with component-level operation, thus necessitating a hierarchical approach to modeling and simulation. This paper presents a hierarchical modeling and simulation method for microelectrofluidic systems (MEFS), in particular, and composite microsystems, in general. High-level stochastic queuing modeling is combined with low-level nodal modeling to support simulation accuracy with low simulation times. Results are reported for a micro-chemical handling system (MCHS). System-level performance analysis is carried out and applied to architectural design optimization.

Abstract—In this paper, we propose a wavelet collocation method with nonlinear companding to generate behavioral models for analog circuits at the system level. During the overall process of circuit modeling, nonlinear function approximation is an important issue to accurately capture the nonideal input–output relations of analog circuit blocks. While a great number of previous research works focus on the high-dimensional top-down design/synthesis model, which involves large analog design spaces, this paper primarily concentrates on the bottom-up verification model requiring both simple representation and high accuracy. Taking advantage of the local support of wavelet bases, a nonlinear companding method is developed to control the modeling error distribution based on system-level simulation requirements. It, in turn, significantly improves the simulation efficiency at the system level. To demonstrate the promising features of the proposed method, two circuit examples, a fourth-order switched-current filter and a voltage-controlled oscillator, are employed to build the behavioral models. Index Terms—Analog circuits, behavioral modeling, nonlinear companding, wavelet collocation method. I.