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14
Redundancy Identification using Transitive Closure
 in Proc. Fifth IEEE Asian Test Symp
, 1996
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A FaultIndependent Transitive Closure Algorithm for Redundancy Identification
 IN PROC. OF THE 16 TH INTERNATIONAL CONF. VLSI DESIGN
, 2003
"... We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as we ..."
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Cited by 8 (5 self)
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We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as well as node fixation. The transitive closure, whose computation now requires a new algorithm, provides many redundant faults in a singlepass analysis. Because of these improvements, we obtain better performance than all previous faultindependent methods at execution speeds that are much faster than any exhaustive ATPG. For example, in the s9234 circuit more than half of the redundant faults are found in just 14 seconds on a Sparc 5. All 34 redundant faults of c6288 are found in one pass. Besides, our single pass procedure can classify faults according to the causes of their redundancy. The weakness of our method, as we illustrate by examples, lies in the lack of a formulation for the observabilities of fanout stems.
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
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Theorems on Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
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There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. Our framework is an implication graph of signal controllabilities and observabilities represented as Boolean variables. Besides the conventional implication edges this graph also contains partial implications implemented by AND nodes. An analysis of the transitive closure (TC) of this graph provides many redundancies. Weaknesses of this procedure are in dealing with the effects of xedvalued variables on TC and the lack of observability relations across fanouts. The fixedvalue theorem adds unconditional edges from all variables to the fixed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identi ed. Besides, our procedure can classify faults according to the causes of their redundancy, namely, unexcitable, unobservable, or undrivable. For the future research, we provide examples of cases where the present method still fails.
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
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A New Testability Calculation Method to Guide RTL Test Generation
 JOURNAL OF ELECTRONIC TESTING: THEORY AND APPLICATIONS
, 2005
"... Current paper presents a unified approach for calculating mixedlevel testability measures. In addition, anew method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision d ..."
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Cited by 1 (1 self)
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Current paper presents a unified approach for calculating mixedlevel testability measures. In addition, anew method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gatelevel test generation. However, works on application of testability measures to guide highlevel test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RTlevel test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RTlevel fault coverage is in correlation with logic level one.
FixedValue and Stem Unobservability Theorems for Logic Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
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There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure (TC). Both complete and partial implications are included. Weaknesses of this procedure areindealing with the e ects of xedvalued variables on TC and the lack of observability relations across fanouts. The xedvalue theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values, or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identified.
Study of VICTOR: A Testability Analysis Algorithm
"... Abstract—VICTOR is a testability analysis algorithm with linear complexity. The algorithm assigns controllability triplet and observability triplet label, weight and size, to every node. The algorithm also defines two operationsselect and merge, for assigning the controllability and observability ..."
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Abstract—VICTOR is a testability analysis algorithm with linear complexity. The algorithm assigns controllability triplet and observability triplet label, weight and size, to every node. The algorithm also defines two operationsselect and merge, for assigning the controllability and observability measures for every node in the circuit. The node label is a symbol indicating the signal dependencies at that point. The node weight is assigned to estimate the chance of reconvergance of fanout branches at that node. The node size signifies the number of tests for controlling or observing the fault at that node. VICTOR is a useful tool in addressing acute problems in test generation for large circuits: minimizing the effort in test generation by removing the redundancy in the circuit design, increasing speed of the testability algorithm. Index Terms—Fast Testability Analysis, VICTOR, Redundancy I.