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Redundancy Identification Using Transitive Closure
 in Proc. of the 5th Asian Test Symp
, 1996
"... We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boole ..."
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Cited by 11 (5 self)
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We analyze all signals of a combinational circuit simultaneously for redundancy. The state of a signal is represented by two binary variables. The first variable is the logic value of the signal. The second variable is the observability status of the signal with respect to all primary outputs. Boolean equations specify local relationships of these variables in a manner similar to the neural network or Boolean satisfiability method. All pairwise terms appearing in these Boolean equations are used to construct an implication graph, for which the transitive closure graph is obtained. Any signal assignments or relations found from the transitive closure are substituted into higherorder terms of the Boolean equations, some of which reduce to pairwise terms. Such cases are iteratively included in the transitive closure until no more reductions are possible. In the final transitive closure, all signals are examined for the following conditions of redundancy: (1) If a signal and its complement imply each other (contradiction) then both stuckat faults on that signal are redundant; (2) If one value implies the other value (fixation) then one of the stuckat faults on that signal is redundant; (3) If the true observability status of a signal implies its own false observability status, then both stuckat faults of that signal are redundant; (4) If a certain value of a signal implies the false observability status, then the corresponding stuckat fault is redundant. Despite the apparent similarities with the transitive closure based ATPG, the present method is quite different. Here transitive closure is computed just once, and not recomputed or updated separately for each fault as required in ATPG. We give ISCAS '85 benchmark results. For c6288, we could identify 31 out of 33 redu...
A FaultIndependent Transitive Closure Algorithm for Redundancy Identification
 IN PROC. OF THE 16 TH INTERNATIONAL CONF. VLSI DESIGN
, 2003
"... We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as we ..."
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Cited by 8 (5 self)
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We present a faultindependent redundancy identification algorithm. The controllabilities and observabilities are defined as Boolean variables and represented on an implication graph. A major enhancement over previously published results is that we include all direct and partial implications, as well as node fixation. The transitive closure, whose computation now requires a new algorithm, provides many redundant faults in a singlepass analysis. Because of these improvements, we obtain better performance than all previous faultindependent methods at execution speeds that are much faster than any exhaustive ATPG. For example, in the s9234 circuit more than half of the redundant faults are found in just 14 seconds on a Sparc 5. All 34 redundant faults of c6288 are found in one pass. Besides, our single pass procedure can classify faults according to the causes of their redundancy. The weakness of our method, as we illustrate by examples, lies in the lack of a formulation for the observabilities of fanout stems.
Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies
 Proc. 18 th International Conf. VLSI Design
, 2005
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 3 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication
Using Contrapositives to Enhance the Implication Graph of Logic Circuits
 in Proc. of the 13 th IEEE North Atalantic Test Workshop
, 2004
"... Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used ..."
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Cited by 1 (1 self)
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Abstract – Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring ” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding ” node. The addition of a single oring node in the implication graph of a Boolean gate eliminates the need for several anding nodes. An ninput gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding nodes graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is new algorithms
Theorems on Redundancy Identification
 in Proc. of the 12th North Atlantic Test Workshop
, 2003
"... Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student ..."
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Cited by 1 (0 self)
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Redundant logic in a digital circuit is often identified as untestable or redundant single stuckat faults. Redundant faults in a combinational circuit are faults that no input patterns can detect [2]. Removal of such faults simplifies the circuit without chang\Lambda Student
A Dynamic Diagnostic Test Generation System for I_DDQ Measurement Based Diagnosis of Bridging FAults
, 1995
"... A paradigm for diagnosis, known as dynamic diagnosis, is defined. A systembased on this paradigm, for I DDQ measurement based diagnosis of bridging faults, is reported. Experimental evaluation of the performance of the system shows it to be substantially superior to existing systems, especially for ..."
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A paradigm for diagnosis, known as dynamic diagnosis, is defined. A systembased on this paradigm, for I DDQ measurement based diagnosis of bridging faults, is reported. Experimental evaluation of the performance of the system shows it to be substantially superior to existing systems, especially for larger circuits. 1 Introduction Given a circuit and the observed faulty response of the circuit, diagnosis(or faultlocation) is the process of locating physical faults which result in the faulty response. Such analysis is used to gather information to improve the fabrication process. There are different approaches for fault diagnosis which includes causeeffect analysis and effectcause analysis [3]. In causeeffect analysis, before diagnosis, simulation is used to determine the possible responses of the circuit, to a given test sequence, in the presence of the targeted faults. These responses, along with the faults which cause them, are stored in a fault dictionary. To locate faults, the ...
A Structural Approach for Space Compaction for Sequential Circuits
, 1999
"... In this paper a new structural method for linear output space compaction for synchronous sequential circuits is presented. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions are determined wi ..."
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In this paper a new structural method for linear output space compaction for synchronous sequential circuits is presented. Based on simple estimates for the probabilities of the existence of sensitized paths from the signal lines to the circuit outputs, optimal output partitions are determined without fault simulation. The method is developed for concurrent checking, but as the experimental results show, it is also eectively applicable in pseudorandom test mode. 1 Introduction As the complexity of VLSI continues to increase the number of input/output pins of ICs are increasing accordingly. For ICs with a large number of outputs, output space compaction is of growing interest since these methods allow the necessary hardware overhead for testing and concurrent checking to be reduced. Until now dierent methods for output space compaction were considered for combinational circuits only. The results obtained in [2], [3], [4], [5], [10], [17] are applicable in test mode. Output sp...
Testing and Builtin SelfTest – A Survey
 A. STEININGER: JOURNAL OF SYSTEMS ARCHITECTURE
"... ..."
FixedValue and Stem Unobservability Theorems for Logic Redundancy Identification
, 2003
"... There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to ..."
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There is a class of implicationbased methods that identify logic redundancy from circuit topology and without any primary input assignment. These methods are less complex than automatic test pattern generation (ATPG) but identify only a subset of all redundancies. This paper provides new results to enlarge this subset. Contributions are a fixedvalue theorem and two theorems on fanout stem unobservability. We represent signal controllabilities and observabilities using an implication graph and its transitive closure (TC). Both complete and partial implications are included. Weaknesses of this procedure areindealing with the e ects of xedvalued variables on TC and the lack of observability relations across fanouts. The xedvalue theorem adds unconditional edges from all variables to the xed variable and then recomputes TC recursively until no new fixed nodes are found. The stem unobservability theorems determine the observability status of a fanout stem from its dominator set, which either has fixed values, or is unobservable. Results are considerably improved from the previously reported implicationbased identi ers. In the c5315 circuit we identify 58 out of 59 redundant faults. All 34 redundant faults of c6288 are identified.