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An Overview of the Formal Specification and Verification of the FM9001 Microprocessor
, 1994
"... This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS ..."
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This document presents the details of the FM9001 development, its specification, and its verification. 1 RESULTS
The Formalization of a Simple Hardware Description Language
 Applied Formal Methods For Correct VLSI Design
, 1989
"... . A hierarchical, occurrenceoriented, combinational hardware description language has been formalized using the BoyerMoore logic. Instead of representing circuits as formulas of a particular logic, combinational circuits are represented by list constants in the BoyerMoore logic. A goodcircuit pr ..."
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. A hierarchical, occurrenceoriented, combinational hardware description language has been formalized using the BoyerMoore logic. Instead of representing circuits as formulas of a particular logic, combinational circuits are represented by list constants in the BoyerMoore logic. A goodcircuit predicate recognizes wellformed circuit descriptions; an interpreter provides the semantics of the language. This approach allows the direct verification of circuit specifications, as well as allowing the verification of circuit generating functions. A circuit generating function for a family of ALUs has been verified using these techniques. 1. Introduction The formalization of a hierarchical, occurrenceoriented, combinational hardware description language (HDL) has been employed to prove the correctness of functions which generate circuits. This formalization was carried out with the BoyerMoore logic and its associated mechanical theorem prover [Boyer & Moore 88]. HDL statements are forma...
Modular Operational Semantic Specification of Transport Triggered Architectures
, 1997
"... The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult. However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided fo ..."
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The formal specification of hardware at the instruction level is a daunting task. The complexity, size and intricacies of most instruction sets makes this task even more difficult. However, the benefits of such a specification can be quite rewarding: a precise, unambiguous description is provided for each instruction, a basis for proving the correctness of code transformations is made available, and the specification can be animated, providing a simulator. This paper proposes a high level structural operational semantic (S.O.S.) specification for the class of transport triggered architectures. These architectures are simple, powerful, flexible and modular and can exploit very fine grained parallelism. The S.O.S. is novel in that it follows the structure of the architecture, and by doing so inherits the modularity of the architecture. 1 INTRODUCTION The precise definition of programming languages is important; ambiguities in programming language definitions were rife before the introdu...
Toward a Super Duper Hardware Tactic
, 1993
"... We present techniques for automating many of the tedious aspects of hardware verification in a higher order logic theorem proving environment. We employ two complementary approaches. The first involves intelligent tactics which incorporate many of the smaller steps currently applied by the user. ..."
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We present techniques for automating many of the tedious aspects of hardware verification in a higher order logic theorem proving environment. We employ two complementary approaches. The first involves intelligent tactics which incorporate many of the smaller steps currently applied by the user. The second uses hardware combinators to partially automate inductive proofs for iterated hardware structures. We envision a system that captures most of this reasoning in one tactic, SuperDuperHWTac. Ideally, users would use this tactic on a goal for proving that a hardware component meets its specification, and get back a proof documented at a level they would have written by hand. This paper presents preliminary work toward SuperDuperHWTac in both the HOL and Nuprl proof development systems. 1 Introduction Higher order logic makes specifying hardware designs natural. Unfortunately, it also makes verification tedious. If verification engineers adopt a specific style for doing hardwa...
Formal Verification of Hardware Synthesis
, 2013
"... Abstract. We report on the implementation of a certified compiler for a highlevel hardware description language (HDL) called FeSi (FEatherweight SynthesIs). FeSi is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. FeSi is defined as a dependently typed deep e ..."
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Abstract. We report on the implementation of a certified compiler for a highlevel hardware description language (HDL) called FeSi (FEatherweight SynthesIs). FeSi is a simplified version of Bluespec, an HDL based on a notion of guarded atomic actions. FeSi is defined as a dependently typed deep embedding in Coq. The target language of the compiler corresponds to a synthesisable subset of Verilog or VHDL. A key aspect of our approach is that input programs to the compiler can be defined and proved correct inside Coq. Then, we use extraction and a Verilog backend (written in OCaml) to get a certified version of a hardware design.